UM012811-0904
eZ8 CPU Instruction Set Description
eZ8 CPU
User Manual
185
TCMX
Test Complement Under Mask using Extended Addressing
TCMX dst, src
Operation
(NOT dst) AND src
Description
This instruction tests selected bits in the destination operand for a logical 1 value. Specify
the bits to be tested by setting a 1 bit in the corresponding bit position in the source oper-
and (the mask). The TCMX instruction complements the destination operand and AND’s
it with the source mask (operand). Check the Zero flag to determine the result. If the Z flag
is set, then the tested bits are 1. When a TCMX operation is completed, the destination and
source operands still contain their original values.
Flags
Attributes
Escaped Mode Addressing
Using Escaped Mode Addressing, address mode ER for the source or destination specifies
a Working Register with 4-bit addressing.
If the high byte of the source or destination address is
EEH
(11101110B), a Working Regis-
ter is inferred. For example, the operand
EE3H
selects Working Register R3. The full 12-
bit address is given by {RP[3:0], RP[7:4], 3H}.
To access Registers on Page EH (addresses
E00H
to
EFFH
), set the Page Pointer, RP[3:0],
to
EH
and set the Working Group Pointer, RP[7:4], to the desired Working Group.
C
Unaffected.
Z
Set if the result is zero; reset otherwise.
S
Set if the result is negative; reset otherwise.
V
Reset to 0.
D
Unaffected.
H
Unaffected.
Mnemonic Destination, Source
Opcode (Hex)
Operand 1
Operand 2
Operand 3
TCMX
ER1, ER2
68
ER2[11:4]
{ER2[3:0], ER1[11:8]}
ER1[7:0]
TCMX
ER1, IM
69
IM
{0H, ER1[11:8]}
ER1[7:0]
