UM012811-0904
eZ8 CPU Instruction Set Summary
eZ8 CPU
User Manual
36
; value
01H
, is the source. The value
01H
is written into the
; Register at address
234H
.
ASSEMBLY LANGUAGE SYNTAX
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as ‘destination, source’. After assembly, the object code usually places
the operands in the order ’source, destination’, but ordering is opcode-dependent. The fol-
lowing instruction examples illustrate the format of some basic assembly instructions and
the resulting object code produced by the assembler. This binary format must be followed
by users that prefer manual program coding or intend to implement their own assembler.
Example 1
: If the contents of Registers
43H
and
08H
are added and the result is stored in
43H
, the assembly syntax and resulting object code is:
Example 2
: In general, when an instruction format requires an 8-bit register address, that
address can specify any register location in the range 0–255 or, using Escaped Mode
Addressing, a Working Register R0–R15. If the contents of Register 43H and Working
Register R8 are added and the result is stored in 43H, the assembly syntax and resulting
object code is:
See the device-specific Product Specification to determine the exact register file range
available. The register file size varies, depending on the device type.
EZ8 CPU INSTRUCTION NOTATION
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that
Table 10 describes.
Table 8. Assembly Language Syntax Example 1
Assembly Language Code
ADD
43H,
08H
(ADD dst, src)
Object Code
04
08
43
(OPC src, dst)
Table 9. Assembly Language Syntax Example 2
Assembly Language Code
ADD
43H,
R8
(ADD dst, src)
Object Code
04
E8
43
(OPC src, dst)
