UM012811-0904
eZ8 CPU Instruction Set Description
eZ8 CPU
User Manual
143
OR
Logical OR
OR dst, src
Operation
dst
←
dst OR src
Description
The source operand is logically OR’ed with the destination operand and the destination
operand stores the result. The contents of the source operand are unaffected. An OR oper-
ation stores a 1-bit when either of the corresponding bits in the two operands is a 1. Other-
wise, the OR operation stores a 0 bit.
Flags
Attributes
Escaped Mode Addressing
Using Escaped Mode Addressing, address modes R or IR can specify a Working Register.
If the high nibble of the source or destination address is
EH
(1110B), a Working Register
is inferred. For example, if Working Register R12 (
CH
) is the desired destination operand,
use
ECH
as the destination operand in the opcode. To access Registers with addresses
E0H
to
EFH
, either set the Working Group Pointer, RP[7:4], to
EH
or use indirect addressing.
C
Unaffected.
Z
Set if the result is zero; reset otherwise.
S
Set if Bit 7 of the result is set; reset otherwise.
V
Reset to 0.
D
Unaffected.
H
Unaffected.
Mnemonic
Destination, Source
Opcode (Hex)
Operand 1
Operand 2
Operand 3
OR
r1, r2
42
{r1, r2}
—
—
OR
r1, @r2
43
{r1, r2}
—
—
OR
R1, R2
44
R2
R1
—
OR
R1, @R2
45
R2
R1
—
OR
R1, IM
46
R1
IM
—
OR
@R1, IM
47
R1
IM
—
