UM012811-0904
eZ8 CPU Instruction Set Description
eZ8 CPU
User Manual
61
ADDX
Add using Extended Addressing
ADDX dst, src
Operation
dst
←
dst + src
Description
The source operand is added to the destination operand. Two’s-complement addition is
performed. The sum is stored in the destination operand. The contents of the source oper-
and are not affected.
Flags
Attributes
Escaped Mode Addressing
Using Escaped Mode Addressing, address mode ER for the source or destination specifies
a Working Register with 4-bit addressing.
If the high byte of the source or destination address is
EEH
(11101110B), a Working Regis-
ter is inferred. For example, the operand EE3H selects Working Register R3. The full 12-
bit address is given by {RP[3:0], RP[7:4], 3H}.
To access Registers on Page EH (addresses
E00H
to
EFFH
), set the Page Pointer, RP[3:0],
to EH and set the Working Group Pointer, RP[7:4], to the desired Working Group.
C
Set if there is a carry from bit 7; reset otherwise.
Z
Set if the result is zero; reset otherwise.
S
Set if the result is negative; reset otherwise.
V
Set if an arithmetic overflow occurs; reset otherwise.
D
Reset to 0.
H
Set if there is a carry from bit 3 of the result; reset otherwise.
Mnemonic Destination, Source
Opcode (Hex)
Operand 1
Operand 2
Operand 3
ADDX
ER1, ER2
08
ER2[11:4]
{ER2[3:0], ER1[11:8]} ER1[7:0]
ADDX
ER1, IM
09
IM
{0H, ER1[11:8]}
ER1[7:0]
