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UM012811-0904

Opcode

Maps

eZ8 CPU

User Manual

201

Figure 24. First Opcode Map

CP

3.3

R2,R1

CP

3.4

IR2,R1

CP

2.3

r1,r2

CP

2.4

r1,Ir2

CPX

4.3

ER2,ER1

CPX

4.3

IM,ER1

CP

3.3

R1,IM

CP

3.4

IR1,IM

RRC

2.2

R1

RRC

2.3

IR1

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Lower Nibble (Hex)

Uppe

r Nibb

le

(

H

e

x

)

BRK

1.2

SRP

2.2

IM

ADD

2.3

r1,r2

ADD

2.4

r1,Ir2

ADD

3.3

R2,R1

ADD

3.4

IR2,R1

ADD

3.3

R1,IM

ADD

3.4

IR1,IM

ADDX

4.3

ER2,ER1

ADDX

4.3

IM,ER1

DJNZ

2.3

r1,X

JR

2.2

cc,X

LD

2.2

r1,IM

JP

3.2

cc,DA

INC

1.2

r1

NOP

1.2

RLC

2.2

R1

RLC

2.3

IR1

ADC

2.3

r1,r2

ADC

2.4

r1,Ir2

ADC

3.3

R2,R1

ADC

3.4

IR2,R1

ADC

3.3

R1,IM

ADC

3.4

IR1,IM

ADCX

4.3

ER2,ER1

ADCX

4.3

IM,ER1

INC

2.2

R1

INC

2.3

IR1

SUB

2.3

r1,r2

SUB

2.4

r1,Ir2

SUB

3.3

R2,R1

SUB

3.4

IR2,R1

SUB

3.3

R1,IM

SUB

3.4

IR1,IM

SUBX

4.3

ER2,ER1

SUBX

4.3

IM,ER1

DEC

2.2

R1

DEC

2.3

IR1

SBC

2.3

r1,r2

SBC

2.4

r1,Ir2

SBC

3.3

R2,R1

SBC

3.4

IR2,R1

SBC

3.3

R1,IM

SBC

3.4

IR1,IM

SBCX

4.3

ER2,ER1

SBCX

4.3

IM,ER1

DA

2.2

R1

DA

2.3

IR1

OR

2.3

r1,r2

OR

2.4

r1,Ir2

OR

3.3

R2,R1

OR

3.4

IR2,R1

OR

3.3

R1,IM

OR

3.4

IR1,IM

ORX

4.3

ER2,ER1

ORX

4.3

IM,ER1

POP

2.2

R1

POP

2.3

IR1

AND

2.3

r1,r2

AND

2.4

r1,Ir2

AND

3.3

R2,R1

AND

3.4

IR2,R1

AND

3.3

R1,IM

AND

3.4

IR1,IM

ANDX

4.3

ER2,ER1

ANDX

4.3

IM,ER1

COM

2.2

R1

COM

2.3

IR1

TCM

2.3

r1,r2

TCM

2.4

r1,Ir2

TCM

3.3

R2,R1

TCM

3.4

IR2,R1

TCM

3.3

R1,IM

TCM

3.4

IR1,IM

TCMX

4.3

ER2,ER1

TCMX

4.3

IM,ER1

PUSH

2.2

R2

PUSH

2.3

IR2

TM

2.3

r1,r2

TM

2.4

r1,Ir2

TM

3.3

R2,R1

TM

3.4

IR2,R1

TM

3.3

R1,IM

TM

3.4

IR1,IM

TMX

4.3

ER2,ER1

TMX

4.3

IM,ER1

DECW

2.5

RR1

DECW

2.6

IR1

LDE

2.5

r1,Irr2

LDEI

2.9

Ir1,Irr2

LDX

3.2

r1,ER2

LDX

3.3

Ir1,ER2

LDX

3.4

IRR2,R1

LDX

3.5

IRR2,IR1

LDX

3.4

r1,rr2,X

LDX

3.4

rr1,r2,X

RL

2.2

R1

RL

2.3

IR1

LDE

2.5

r2,Irr1

LDEI

2.9

Ir2,Irr1

LDX

3.2

r2,ER1

LDX

3.3

Ir2,ER1

LDX

3.4

R2,IRR1

LDX

3.5

IR2,IRR1

LEA

3.3

r1,r2,X

LEA

3.5

rr1,rr2,X

INCW

2.5

RR1

INCW

2.6

IR1

CLR

2.2

R1

CLR

2.3

IR1

XOR

2.3

r1,r2

XOR

2.4

r1,Ir2

XOR

3.3

R2,R1

XOR

3.4

IR2,R1

XOR

3.3

R1,IM

XOR

3.4

IR1,IM

XORX

4.3

ER2,ER1

XORX

4.3

IM,ER1

LDC

2.5

r1,Irr2

LDCI

2.9

Ir1,Irr2

LDC

2.5

r2,Irr1

LDCI

2.9

Ir2,Irr1

JP

2.3

IRR1

LDC

2.9

Ir1,Irr2

LD

3.3

r1,r2,X

PUSHX

3.2

ER2

SRA

2.2

R1

SRA

2.3

IR1

POPX

3.2

ER1

LD

3.4

r2,r1,X

CALL

2.6

IRR1

BSWAP

2.2

R1

CALL

3.3

DA

LD

3.2

R2,R1

LD

3.3

IR2,R1

BIT

2.2

p,b,r1

LD

2.3

r1,Ir2

LDX

4.2

ER2,ER1

LDX

4.2

IM,ER1

LD

3.2

R1,IM

LD

3.3

IR1,IM

RR

2.2

R1

RR

2.3

IR1

MULT

2.8

RR1

LD

3.3

R2,IR1

TRAP

2.6

Vector

LD

2.3

Ir1,r2

BTJ

3.3

p,b,r1,X

BTJ

3.4

p,b,Ir1,X

SWAP

2.2

R1

SWAP

2.3

IR1

RCF

1.2

WDT

1.2

STOP

1.2

HALT

1.2

DI

1.2

EI

1.2

RET

1.4

IRET

1.5

SCF

1.2

CCF

1.2

Opcode

See 2nd

Map

1,2

ATM

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Summary of Contents for eZ8

Page 1: ...eZ8 CPU UM012811 0904 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 3432 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com User Manual...

Page 2: ...is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DO...

Page 3: ...Compatibility 9 Overview 9 Assembly Language Compatibility 9 New Instructions 9 Relocation of the eZ8 CPU Control Registers 12 Stack Pointer Compatibility 12 Reset Compatibility 12 Interrupt Compatib...

Page 4: ...ocessing 33 Software Interrupt Generation 33 Illegal Instruction Traps 34 Description 34 eZ8 CPU Instruction Set Summary 35 Assembly Language Programming Introduction 35 Assembly Language Syntax 36 eZ...

Page 5: ...gure 10 Register Addressing Using 4 Bit Addresses 23 Figure 11 Indirect Register Addressing to Register File 24 Figure 12 Indirect Register Addressing to Program or Data Memory 25 Figure 13 Indexed Re...

Page 6: ...ntax Example 2 36 Table 10 Notational Shorthand 37 Table 11 Additional Symbols 38 Table 12 Arithmetic Instructions 39 Table 13 Bit Manipulation Instructions 39 Table 14 Block Transfer Instructions 40...

Page 7: ...tended Audience This document is written for ZiLOG customers who are experienced at working with microprocessors or in writing assembly code or compilers Manual Organization The User Manual is divided...

Page 8: ...tions including mnemonic definitions and a summary of the User Manual instruction set Opcode Maps Presents a detailed diagram of each opcode table Opcodes Listed Numerically Provides an easy reference...

Page 9: ...egister values taken from the Register Pointer RP and Working Register R1 0H is the most significant nibble 4 bit value of the 12 bit register and R1 3 0 is the least significant nibble of the 12 bit...

Page 10: ...eneral text Example 1 Stop mode Example 2 The receiver forces the SCL line to Low The Master can generate a Stop condition to abort the transfer Use of All Uppercase Letters The use of all uppercase l...

Page 11: ...required program memory Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with Z8 assembly instruction set Expanded internal Register File al...

Page 12: ...lows 1 Fetch the opcode 2 Determine the operand size number of bytes 3 Fetch the operands 4 Present the opcode and operands to the Instruction State Machine The Fetch Unit is pipelined and operates se...

Page 13: ...e three bytes The Execution Unit is idle during a delay cycle PROGRAM COUNTER The Program Counter contains a 16 bit counter and a 16 bit adder The Program Counter monitors the address of the current m...

Page 14: ...s There are 16 Working Register Groups per page For more information on the Register File please refer to the sec tion Address Space on page 13 Flags Register The Flags Register contains the status in...

Page 15: ...hanging the value of the Carry Flag Complement Carry Flag CCF Reset Carry Flag RCF Set Carry Flag SCF Zero Flag For arithmetic and logical operations the Zero Z flag is 1 if the result is 0 Otherwise...

Page 16: ...inary Coded Decimal BCD arithmetic opera tions Because the algorithm for correcting BCD operations is different for addition and subtraction this flag specifies the type of instruction that was last e...

Page 17: ...er in Register Table 2 Condition Codes Binary Hex Assembly Mnemonic Definition Flag Test Operation 0000 0 F Always False 0001 1 LT Less Than S XOR V 1 0010 2 LE Less Than or Equal Z OR S XOR V 1 0011...

Page 18: ...22H and 123H The value is stored as 0001H The most significant byte 00H is stored in the lowest memory address at 122H The least significant byte 01H is stored in the higher memory address at 123H Thi...

Page 19: ...Dog Timer Enable During HALT Mode at opcode 4FH Users with existing Z8 assem bly code can easily compile their code to use the eZ8 CPU The assembler for the eZ8 CPU is available for download from www...

Page 20: ...ffective Address MULT 8 bit X 8 bit multiply with 16 bit result SRL Shift Right Logical TRAP Software Trap Table 4 New Extended Addressing Instructions Mnemonic Instruction Description ADCX Add with C...

Page 21: ...2 have been removed from the opcode map as they are now subsets of the LD instruction opcode E4 using Escaped mode address ing In the Z8 CPU these instructions used opcodes 08H through F8H and 09H thr...

Page 22: ...of the stack to be placed at any address from 000H to EFFH where general purpose registers are available Refer to the device specific Product Specification for available Register File addresses All st...

Page 23: ...n defined as destinations The architecture of the eZ8 CPU allows all general purpose registers to function as accumulators address pointers index registers stack areas or scratch pad memory Some eZ8 C...

Page 24: ...ear address space using 12 bit address ing mode as sixteen 256 byte Register Pages using 8 bit addressing mode or as sixteen 16 byte Working Register Groups per Register Page using 4 bit addressing mo...

Page 25: ...Extended Addressing instructions have been added to allow easier register access across page boundaries Page Mode Addressing of the Register File In Page mode the Register File is divided into sixtee...

Page 26: ...and the Working Group Pointer to form the full 12 bit address RP 3 0 RP 7 4 Address 3 0 Figure 4 illustrates this operation Figure 4 Working Register Addressing Example Because Working Registers can t...

Page 27: ...y write to a Read Only regis ter To determine which control registers allow either Read Only or Write Only access refer to the device specific Product Specification PROGRAM MEMORY The eZ8 CPU can acce...

Page 28: ...he LDE and LDEI instructions Valid addresses for the Data Memory are from 0000H to FFFFH Individual products containing the eZ8 CPU support varying amounts of Data Memory Refer to the device specific...

Page 29: ...ing execution of a Return RET Interrupts and Traps either the TRAP instruction or an Illegal Instruction Trap save the contents of the Pro gram Counter and the Flags Register on the stack The Interrup...

Page 30: ...ered address in the range of 0 2 14 Register Pairs use 8 bit addresses and must be specified as an even numbered address in the range of 0 2 254 In the following definitions of Addressing Modes the us...

Page 31: ...g 8 bit addressing The upper 4 bits of the 12 bit address is provided by the Page Pointer RP 3 0 The full 12 bit address is given by RP 3 0 Address 7 0 Figure 9 illustrates using 8 bit addressing the...

Page 32: ...oint to one of the 16 possible Working Registers within the current Working Register Group This 4 bit address is combined with the Page Pointer RP 3 0 and the Working Group Pointer RP 7 4 to form the...

Page 33: ...sing Escaped Mode Addressing with 12 bit Addresses Using Escaped Mode Addressing address mode ER for the source or destination can spec ify a Working Register with 4 bit addressing If the high byte of...

Page 34: ...s point to a Register File Program Memory or an Data Memory location When accessing Program Memory or Data Memory Register Pairs or Working Register Pairs hold the 16 bit addresses Figure 11 Indirect...

Page 35: ...egister offset by an 8 bit Signed Index value Figure 13 illustrates Indexed Addressing One 8 bit Program Memory Address dst One Operand Instruction Example Opcode dst 7 0 Destination Register File Reg...

Page 36: ...Jump JP and JP cc and Call CALL instruc tions use Direct Addressing The 16 bit Direct Address is written to the Program Counter Two 4 bit Program Memory Address dst src Two Operand Instruction Example...

Page 37: ...the Program Counter obtains the address of the next instruction to be exe cuted Prior to the addition operation the Program Counter contains the address of the instruction immediately following the cu...

Page 38: ...operand value used by the instruction is the value supplied in the operand field itself Because an immediate operand is part of the instruction it is always located in the Pro gram Memory address spac...

Page 39: ...Z8 CPU User Manual 29 Figure 16 Immediate Data Addressing Program Memory Two Operand Instruction Example Opcode dst Immediate Data Register File 12 bit address is RP 3 0 dst 7 0 Destination Register 8...

Page 40: ...ion to determine available interrupt sources internal and external triggering edge options and exact programming details INTERRUPT ENABLE AND DISABLE Interrupts are globally enabled and disabled by ex...

Page 41: ...k Pointer and the contents of the stack Figure 18 provides an example of the Program Memory during interrupt oper ation In the example of Figure 18 the Interrupt Vector is located at address 0014H in...

Page 42: ...the Interrupt Enable Register information with new masks to disable lower priority interrupts 3 Execute an EI instruction to enable the interrupts 4 Proceed with the interrupt service routine processi...

Page 43: ...ce routine code here AND IRQ1 1101111B Clear the interrupt request in Bit 5 of IRQ1 RET Return to address following the CALL Refer to the device specific Product Specification for information on the I...

Page 44: ...stored at Pro gram Memory address 0006H The least significant byte LSB of the Illegal Instruction Trap Vector is stored at Program Memory address 0007H The 16 bit Illegal Instruction Trap Vector repla...

Page 45: ...her instructions The assembly language also includes assembler directives that supplement the machine instruction The assembler directives or pseudo ops are not translated into a machine instruction T...

Page 46: ...ntax and resulting object code is Example 2 In general when an instruction format requires an 8 bit register address that address can specify any register location in the range 0 255 or using Escaped...

Page 47: ...gister Rn n 0 15 IR Indirect Register Reg Reg represents a number in the range of 00H to FFH Irr Indirect Working Register Pair RRp p 0 2 4 6 8 10 12 or 14 IRR Indirect Register Pair Reg Reg represent...

Page 48: ...CPU instructions can be divided functionally into the following groups Arithmetic Bit Manipulation Block Transfer CPU Control Load Logical Program Control Rotate and Shift Table 11 Additional Symbols...

Page 49: ...rc Add with Carry ADCX dst src Add with Carry using Extended Addressing ADD dst src Add ADDX dst src Add using Extended Addressing CP dst src Compare CPC dst src Compare with Carry CPCX dst src Compar...

Page 50: ...ions Mnemonic Operands Instruction LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDEI dst src Load External Data to from Data Memory and Auto Increment Addresses Table...

Page 51: ...ry and Auto Increment Addresses LDWX dst src Load Word using Extended Addressing LDX dst src Load using Extended Addressing LEA dst X src Load Effective Address POP dst Pop POPX dst Pop using Extended...

Page 52: ...dst Call Procedure DJNZ dst dst RA Decrement and Jump Non Zero IRET Interrupt Return JP dst Jump JP cc dst Jump Conditional JR DA Jump Relative JR cc DA Jump Relative Conditional RET Return TRAP vecto...

Page 53: ...on Table 20 eZ8 CPU Instruction Summary Assembly Mnemonic Symbolic Operation Address Mode Opcode s Hex Flags Fetch Cycles Instr Cycles dst src C Z S V D H ADC dst src dst dst src C r r 12 0 2 3 r Ir 1...

Page 54: ...00 1 2 BSET bit dst dst bit 1 r E2 0 2 2 BSWAP dst dst 7 0 dst 0 7 R D5 X 0 2 2 BTJ p bit src dst if src bit p PC PC X r F6 3 3 Ir F7 3 4 BTJNZ bit src dst if src bit 1 PC PC X r F6 3 3 Ir F7 3 4 BTJZ...

Page 55: ...F A5 4 4 R IM 1F A6 4 3 IR IM 1F A7 4 4 CPCX dst src dst src C ER ER 1F A8 5 3 ER IM 1F A9 5 3 CPX dst src dst src ER ER A8 4 3 ER IM A9 4 3 DA dst dst DA dst R 40 X 2 2 IR 41 2 3 DEC dst dst dst 1 R...

Page 56: ...st dst 1 RR A0 2 5 IR A1 2 6 IRET FLAGS SP SP SP 1 PC SP SP SP 2 IRQCTL 7 1 BF 1 5 JP dst PC dst DA 8D 3 2 IRR C4 2 3 JP cc dst if cc is true PC dst DA 0D FD 3 2 JR dst PC PC X RA 8B 2 2 JR cc dst if...

Page 57: ...c dst src r r 1 rr rr 1 Ir Irr C3 2 9 Irr Ir D3 2 9 LDE dst src dst src r Irr 82 2 5 Irr r 92 2 5 LDEI dst src dst src r r 1 rr rr 1 Ir Irr 83 2 9 Irr Ir 93 2 9 LDWX dst src dst src ER ER 1FE8 5 4 Tab...

Page 58: ...st dst 15 0 dst 15 8 dst 7 0 RR F4 2 8 NOP No operation 0F 1 2 OR dst src dst dst OR src r r 42 0 2 3 r Ir 43 2 4 R R 44 3 3 R IR 45 3 4 R IM 46 3 3 IR IM 47 3 4 ORX dst src dst dst OR src ER ER 48 0...

Page 59: ...91 2 3 RLC dst R 10 2 2 IR 11 2 3 RR dst R E0 2 2 IR E1 2 3 RRC dst R C0 2 2 IR C1 2 3 Table 20 eZ8 CPU Instruction Summary Continued Assembly Mnemonic Symbolic Operation Address Mode Opcode s Hex Fl...

Page 60: ...2 2 STOP Stop Mode 6F 1 2 SUB dst src dst dst src r r 22 1 2 3 r Ir 23 2 4 R R 24 3 3 R IR 25 3 4 R IM 26 3 3 IR IM 27 3 4 SUBX dst src dst dst src ER ER 28 1 4 3 ER IM 29 4 3 Table 20 eZ8 CPU Instruc...

Page 61: ...src r r 72 0 2 3 r Ir 73 2 4 R R 74 3 3 R IR 75 3 4 R IM 76 3 3 IR IM 77 3 4 TMX dst src dst AND src ER ER 78 0 4 3 ER IM 79 4 3 TRAP Vector SP SP 2 SP PC SP SP 1 SP FLAGS PC Vector Vector F2 2 6 WDT...

Page 62: ...IR IM B7 3 4 XORX dst src dst dst XOR src ER ER B8 0 4 3 ER IM B9 4 3 Table 20 eZ8 CPU Instruction Summary Continued Assembly Mnemonic Symbolic Operation Address Mode Opcode s Hex Flags Fetch Cycles I...

Page 63: ...gure 19 illustrates an example layout of the instruction pages that follow Mnemonic Description Simplified description of assembly coding Operation Symbolic description of the operation performed Desc...

Page 64: ...of the source operand are not affected In multiple precision multi byte arithmetic this instruction permits the carry from the addition of low order byte operations to be car ried into the addition of...

Page 65: ...ns the value 20H the statement ADC R3 R11 Object Code 12 3B leaves the value 37H in Working Register R3 and clears the C Z S V D and H flags If Working Register R15 contains the value 16H the Carry fl...

Page 66: ...is set Working Register R3 contains the value 10H and Register 10H contains the value 01H the statement ADC 4BH R3 Object Code 15 E3 4B leaves the value 84H in Register 4BH sets the S flag and clears...

Page 67: ...ing address mode ER for the source or destination can spec ify a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is in...

Page 68: ...e C Z S V and D flags Using Escaped Mode Addressing if Working Register R4 contains the value 2EH the Carry flag is set and Register B12H contains the value 1BH the statement ADCX EE4H B12H Object Cod...

Page 69: ...inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with addresses E0H to EFH either set the Working...

Page 70: ...2H contains the value 1BH the statement ADD 34H 12H Object Code 04 12 34 leaves the value 49H in Register 34H sets the H flag and clears the C Z S V and D flags Using Escaped Mode Addressing if Regist...

Page 71: ...address is EEH 11101110B a Working Regis ter is inferred For example the operand EE3H selects Working Register R3 The full 12 bit address is given by RP 3 0 RP 7 4 3H To access Registers on Page EH ad...

Page 72: ...g and clears the C Z S V and D flags Using Escaped Mode Addressing if Working Register R4 contains the value 2EH and Register B12H contains the value 1BH the statement ADDX EE4H B12H Object Code 08 B1...

Page 73: ...IR specify a Working Register If the high nibble of the source or destination address is EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination oper...

Page 74: ...Register 42H contains the value 0AH 00001010 the statement AND 3AH 42H Object Code 54 42 3A leaves the value 00H 00000000B in Register 3AH sets the Z flag and clears the V and S flags Using Escaped M...

Page 75: ...UM012811 0904 eZ8 CPU Instruction Set Description eZ8 CPU User Manual 65 leaves the value 04H 00000100B in Register 3EH and clears the Z V and S flags...

Page 76: ...or destination can spec ify a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is inferred For example the operand EE3...

Page 77: ...he value 0AH 00001010 the statement ANDX 93AH 142H Object Code 58 14 29 3A leaves the value 00H 00000000B in Register 93AH sets the Z flag and the V and S flags clear If Register D7AH contains the val...

Page 78: ...s During execution of these next 3 instructions all interrupts and DMA requests are prevented This allows operations to be performed on multi byte registers and memory locations that could be changed...

Page 79: ...butes Example If Working Register R7 contains the value 38H 00111000B the statement BCLR 4 R7 Object Code E2 47 leaves the value 28H 00101000B in Working Register R7 and clears the V flag C Unaffected...

Page 80: ...ement BIT 0 4 R7 Object Code E2 47 leaves the value 28H 00101000B in Working Register R7 and clears the V flag If Working Register R7 contains the value 38H 00111000B the statement BIT 1 2 R7 Object C...

Page 81: ...ption Executes a on chip debugger break at this address Refer to the device specific Product Specification for information regarding the on chip debugger Flags Attributes C Unaffected Z Unaffected S U...

Page 82: ...tributes Example If Working Register R7 contains the value 38H 00111000B the statement BSET 2 R7 Object Code E2 A7 leaves the value 3CH 00111010B in Working Register R7 and clears the V flag C Unaffec...

Page 83: ...Working Register is inferred For exam ple if Working Register R12 CH is the desired destination operand use ECH as the desti nation operand in the opcode To access Registers with addresses E0H to EFH...

Page 84: ...UM012811 0904 eZ8 CPU Instruction Set Description eZ8 CPU User Manual 74 leaves the value CAH 11001010B in Register 27 sets the S flag and clears the V flag The C flag is undefined...

Page 85: ...the source is equal to the polarity p the signed dis placement X is added to the Program Counter which causes a jump The displacement value can be from 128 to 127 This instruction tests only a single...

Page 86: ...ected If Working Register R7 contains the value 20H 00100000B the BTJ instruction that begins the following code segment C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected M...

Page 87: ...e eZ8 CPU assembler automatically calculates the desired displacement value of 01H allowing the Program Counter to skip the one byte HALT instruction and jump to the NEXT label that identifies the LD...

Page 88: ...register pointed to by the source operand is com pared with the a logical 1 If the selected bit is 1 the signed destination displacement X is added to the Program Counter that causes a jump The displ...

Page 89: ...Program Counter to skip the one byte HALT instruction and jump to the NEXT label that identifies the LD instruction address The flags are unaffected If Working Register R7 contains the value 20H 0010...

Page 90: ...king Register R7 fails the test for a 1 The next instruction executed after the BTJNZ is the HALT instruction The flags are unaffected Assembly Code Object Code BTJNZ 3 r7 NEXT F6 B7 01 HALT 7F NEXT T...

Page 91: ...register pointed to by the source operand is com pared with a logical 0 If the selected bit is 0 the signed destination displacement X is added to the Program Counter that causes a jump The displaceme...

Page 92: ...Program Counter to skip the one byte HALT instruction and jump to the NEXT label that identifies the LD instruction address The flags are unaffected If Working Register R7 contains the value 20H 0010...

Page 93: ...rking Register R7 fails the test for a 0 The next instruction executed after the BTJZ is the HALT instruction The flags are unaffected Assembly Code Object Code BTJZ 5 r7 NEXT F6 57 01 HALT 7F NEXT Th...

Page 94: ...to the original program flow RET pops the top of the stack and replaces the original value into the Program Counter Flags Attributes Escaped Mode Addressing Using Escaped Mode Addressing address mode...

Page 95: ...oints to the address of the first statement in the called procedure to be executed The flags are unaffected If the contents of the Program Counter are 1A47H and the contents of the Stack Pointer are 3...

Page 96: ...e Carry C flag is complemented If C 1 it is 0 If C 0 it is 1 Flags Attributes Example If the Carry flag contains a 0 the statement CCF Object Code EF sets the Carry flag to 1 C Complemented Z Unaffect...

Page 97: ...For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with addresses E0H to EFH either set the Working Group Po...

Page 98: ...eZ8 CPU Instruction Set Description eZ8 CPU User Manual 88 If Register A5H contains the value 23H and Register 23H contains the value FCH the statement CLR A5H Object Code B1 A5 leaves the value 00H i...

Page 99: ...d For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with addresses E0H to EFH either set the Working Group...

Page 100: ...eZ8 CPU User Manual 90 If Register 08H contains the value 24H and Register 24H contains the value FFH 11111111B the statement COM 08H Object Code 61 08 leaves the value 00H 00000000B in Register 24H s...

Page 101: ...ddress is EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with ad...

Page 102: ...egister 34H contains the value 2EH and Register 12H contains the value 1BH the statement CP 34H 12H Object Code A4 12 34 clears the C Z S and V flags If Register 4BH contains the value 82H Working Reg...

Page 103: ...gh nibble of the source or destination address is EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand i...

Page 104: ...H and Register 12H contains the value 1BH and the Carry Flag is 1 the statement CPC 34H 12H Object Code 1F A4 12 34 clears the C Z S and V flags If Register 4BH contains the value 82H Working Register...

Page 105: ...tion can spec ify a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is inferred For example the operand EE3H selects W...

Page 106: ...ontains the value 20H and the Carry flag is 1 the statement CPCX AB3 911 Object Code 1F A8 91 1A B3 sets the C and S flags and clears the Z and V flags If Register 26CH contains the value 2AH the Carr...

Page 107: ...r destination address is EEH 11101110B a Working Reg ister is inferred For example the operand EE3H selects Working Register R3 The full 12 bit address is given by RP 3 0 RP 7 4 3H To access Registers...

Page 108: ...If Register AB3H contains 16H and Register 911H contains 20H the statement CPX AB3 911 Object Code A8 3B sets the C and S flags and clears the Z and V flags If Register 26CH contains 2AH the statement...

Page 109: ...the operation performed If the destination operand is not the result of a valid addition or subtraction of BCD digits the operation is undefined Table 21 Operation of the DAA Instruction Carry Bits 7...

Page 110: ...BCD value 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic If the result of the add...

Page 111: ...as the destination operand in the opcode To access Registers with addresses E0H to EFH either set the Working Group Pointer RP 7 4 to EH or use indirect addressing Examples If Working Register R10 co...

Page 112: ...UM012811 0904 eZ8 CPU Instruction Set Description eZ8 CPU User Manual 102 DEC B3H Object Code 31 B3 leaves the value 00H in Register CBH sets the Z flag and clears the V and S flags...

Page 113: ...IR can specify a Working Register If the high nibble of the source or destination address is EH 1110B a Working Register or Pair is inferred For example if Working Register Pair R12 and R13 with base...

Page 114: ...tement DECW 30H Object Code 80 30 leaves the value 0AF1H in Register Pair 30H and 31H and clears the Z V and S flags If Working Register R0 contains 30H and Register Pair 30H and 31H contain the value...

Page 115: ...r Flags Attributes Example If IRQCTL Interrupt Control register FCFH contains 80H 10000000B interrupts are globally enabled Upon execution of the DI command the statement DI Object Code 8FH the IRQCTL...

Page 116: ...ents of the Working Register are not zero after being decremented then the relative address is added to the Program Counter and control passes to the statement whose address is now in the Program Coun...

Page 117: ...nter with 18d 12H 2 Load the R4 source pointer 3 Load the R2 destination pointer 4 Set up the loop to perform moves 5 End loop with DJNZ Mnemonic Destination Address Opcode Hex Operand 1 Operand 2 Ope...

Page 118: ...outine is as follows Ld R6 12H Load counter with 12H 18d Ld R4 36H Load source pointer Ld R2 24H Load destination pointer LOOP Ld R3 R4 Load byte in R3 from source Ld R2 R3 Write byte to destination d...

Page 119: ...butes Example If IRQCTL Interrupt Control register FCFH contains the value 00H 00000000B inter rupts are globally disabled Upon execution of the EI command the statement EI Object Code 9FH the IRQCTL...

Page 120: ...eZ8 CPU into HALT mode Refer to the device specific Product Specification for information on HALT mode operation Flags Attributes Example The statement HALT Object Code 7F places the eZ8 CPU in HALT m...

Page 121: ...st Operation dst dst 1 Description The contents of the destination operand are incremented by one Flags C Unaffected Z Set if the result is zero reset otherwise S Set if Bit 7 of the result is set res...

Page 122: ...f Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with addresses E0H to EFH either set the Working Group Pointer RP 7 4...

Page 123: ...orking Register R10 and clears the Z V and S flags If Register B3H contains the value CBH the statement INC B3H Object Code 20 B3 leaves the value CCH in Register CBH sets the S flag and clears the Z...

Page 124: ...IR can specify a Working Register If the high nibble of the source or destination address is EH 1110B a Working Register or Pair is inferred For example if Working Register Pair R12 and R13 with base...

Page 125: ...tement INCW 30H Object Code A0 30 leaves the value 0AF3H in Register Pair 30H and 31H and clears the Z V and S flags If Working Register R0 contains 30H and Register Pair 30H and 31H contain the value...

Page 126: ...s 6FH and Register 47H contains E4H the statement IRET Object Code BF restores the Flags Register FCH with the value 00H restores the PC with the value 6FE4H re enables the interrupts and sets the Sta...

Page 127: ...of the source or destination address is EH 1110B a Working Register Pair is inferred For example if Working Register Pair R12 and R13 with base address CH is the desired destination operand use ECH as...

Page 128: ...UM012811 0904 eZ8 CPU Instruction Set Description eZ8 CPU User Manual 118 replaces the contents of the PC with the value 3F45H and transfers program control to that location...

Page 129: ...1 PC dst Description A conditional jump transfers program control to the destination address if the condition specified by cc is true Otherwise the instruction following the JP instruction is executed...

Page 130: ...ement following the JP instruction Mnemonic Condition Code Destination Address Opcode Hex Operand 1 Operand 2 Operand 3 JP F DA 0D DA 15 18 DA 7 0 JP LT DA 1D DA 15 8 DA 7 0 JP LE DA 2D DA 15 8 DA 7 0...

Page 131: ...s added to the Program Counter and control passes to the instruction located at the address specified by the Program Counter The range of the rela tive address is 127 to 128 and the original value of...

Page 132: ...relative address offset is added to the Pro gram Counter and control passes to the instruction located at the address specified by the Program Counter SeeSection Condition Codes Plain on page 6 for co...

Page 133: ...nic Condition Code Address Opcode Hex Operand 1 Operand 2 Operand 3 JR F DA 0B X JR LT DA 1B X JR LE DA 2B X JR ULE DA 3B X JR OV DA 4B X JR MI DA 5B X JR Z DA 6B X JR C DA 7B X JR T DA 8B X JR GE DA...

Page 134: ...ual 124 LD Load LD dst src Operation dst src Description The contents of the source operand are loaded into the destination operand The contents of the source operand are unaffected Flags C Unaffected...

Page 135: ...de To access Registers with addresses E0H to EFH either set the Working Group Pointer RP 7 4 to EH or use indirect addressing Mnemonic Destination Source Opcode Hex Operand 1 Operand 2 Operand 3 LD r1...

Page 136: ...s the value 34H and Register 34H contains the value FFH the statement LD R13 R12 Object Code E3 DC loads the value FFH into Working Register R13 The contents of Working Register R12 and Register R34 a...

Page 137: ...r 45H contains the value FFH the statement LD 34H 45H Object Code F5 45 34 loads the value FFH into Register CFH The contents of Register 34H and Register 45H are not affected If Working Register R0 c...

Page 138: ...g Register Pair R6 and R7 contain the value 30A2H and Program Memory location 30A2H contains the value 22H the statement LDC R2 RR6 Object Code C2 26 loads the value 22H into Working Register R2 The v...

Page 139: ...UM012811 0904 eZ8 CPU Instruction Set Description eZ8 CPU User Manual 129 loads the value 22H into Program Memory location 10A2H The value of Working Register R2 is unchanged by the load...

Page 140: ...ation is specified by a Working Register Pair and the address of the Register File location is specified by Working Register The contents of the source location are loaded into the destination locatio...

Page 141: ...C3 26 loads the value BCH into Register 21H Working Register Pair RR6 increments to 30A4H and Working Register R2 increments to 22H If Working Register R2 contains 20H Register 20H contains 22H Regis...

Page 142: ...and R7 contain the value 40A2H and Data Memory location 40A2H contains the value 22H the statement LDE R2 RR6 Object Code 82 26 loads the value 22H into Working Register R2 The value of Data Memory lo...

Page 143: ...ry location is specified by a Working Register Pair and the address of the Register File location is specified by a Working Register The contents of the source location are loaded into the destination...

Page 144: ...e 83 26 loads the value C3H into Register 23H Working Register Pair RR6 increments to 404CH and Working Register R2 increments to 24H If Working Register R2 contains the value 22H Register 22H contain...

Page 145: ...he source or destination can specify a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is inferred For example the ope...

Page 146: ...cted Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected Mnemonic Destination Source Opcode Hex Operand 1 Operand 2 Operand 3 LDX r1 ER2 84 r1 ER2 11 8 ER2 7 0 LDX r1 ER2 85 r1 ER2 11 8 E...

Page 147: ...tion can specify a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is inferred For example the operand EE3H selects Wo...

Page 148: ...loads the destination Working Register with a value of the Source Regis ter plus the signed displacement X where X is a signed displacement from 127 to 128 Flags Attributes C Unaffected Z Unaffected...

Page 149: ...affected If Working Register R8 contains the value 22H and Working Register R9 contains the value ABH 16 bit value of 22ABH stored in Working Register Pair RR8 the statement LEA RR14 79 RR8 Object Cod...

Page 150: ...estination address is EH 1110B a Working Register Pair is inferred For example if Working Register Pair R12 and R13 with base address CH is the desired destination operand use ECH as the destination o...

Page 151: ...Description eZ8 CPU User Manual 141 gives a result of 2B72H stores the most significant byte of the result 2BH in Working Register R4 and stores the least significant byte of the result 72H in Working...

Page 152: ...NOP Operation None Description No action is performed by this instruction It is typically used as a cycle timing delay Flags Attributes C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffecte...

Page 153: ...s modes R or IR can specify a Working Register If the high nibble of the source or destination address is EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired...

Page 154: ...0101B and Register 42H contains the value 0AH 00001010 the statement OR 3AH 42H Object Code 44 42 3A leaves the value FFH 11111111B in Register 3AH sets the S flag and clears the Z and V flags If Work...

Page 155: ...can spec ify a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is inferred For example the operand EE3H selects Worki...

Page 156: ...ins the value 0AH 00001010 the statement ORX 93AH 142H Object Code 48 14 29 3A leaves the value FFH 11111111B in Register 93AH sets the S flag and clears the Z and V flags If Register D7AH contains th...

Page 157: ...address modes R or IR specifies a Working Register If the destination address is prefixed by EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination...

Page 158: ...34H After the POP operation the Stack Pointer contains 71H The contents of Register 70 are not affected If the Stack Pointer control Registers FFEH and FFFH contains the value 0080H memory location 0...

Page 159: ...Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Reg ister is inferred For example the operand EE3H selects Working Register R3...

Page 160: ...nter control Registers FFEH and FFFH contains the value D70H and Register D70H contains the value 44H the statement POPX 345H Object Code D8 34 50 loads the value 44H into Register 345H After the POP...

Page 161: ...Mode Addressing address modes R or IR can specify a Working Register If the source address is prefixed by EH 1110B a Working Register is inferred For exam ple if Working Register R12 CH is the desire...

Page 162: ...ter contains the value D1FH If the Stack Pointer contains the value E61H and Working Register R4 contains FCH the statement PUSH R4 Object Code 71 E4 stores the contents of Register FCH in location E6...

Page 163: ...address mode ER can specify a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Reg ister is inferred For example the operand EE3H...

Page 164: ...ription eZ8 CPU User Manual 154 Example If the Stack Pointer contains D24H the statement PUSHX FCAH Object Code C8 FC A0 stores the contents of Register FCAH in location D23H After the PUSHX operation...

Page 165: ...arry C flag resets to 0 regardless of its previous value Flags Attributes Example If the Carry flag is currently set the statement RCF Object Code CF resets the Carry flag to 0 C Reset to 0 Z Unaffect...

Page 166: ...countered with a POP instruction to guarantee the Stack Pointer is at the correct location when the RET instruction is executed Otherwise the wrong address loads into the Program Counter and the progr...

Page 167: ...g Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with addresses E0H to EFH either s...

Page 168: ...C6H Object Code 90 C6 leaves the value 11H 00010001B in Register C6H sets the C and V flags and clears the S and Z flags If the contents of Register C6H are 88H and the contents of Register 88H are 44...

Page 169: ...prefixed by EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with...

Page 170: ...C6 Object Code 10 C6 leaves Register C6 with the value 1EH 00011110B sets the C and V flags and clears S and Z flags If the Carry flag is reset Working Register R4 contains the value C6H and Register...

Page 171: ...Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with addresses E0H to EFH either se...

Page 172: ...e statement RR R6 Object Code E0 E6 leaves the value 98H 10011000 in Working Register R6 sets the C V and S flags and clears the Z flag If Register C6 contains the value 31H and Register 31H contains...

Page 173: ...prefixed by EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Registers with...

Page 174: ...tatement RRC C6H Object Code C0 C6 leaves the value 6EH 01101110B in Register C6H sets the C and V flags and clears the Z and S flags If Register 2C contains the value EDH Register EDH contains the va...

Page 175: ...de Addressing address modes R or IR can specify a Working Register If the high nibble of the source or destination address is EH 1110B a Working Register is inferred For example if Working Register R1...

Page 176: ...and Register 12H contains the value 1BH the statement SBC 34H 12H Object Code 34 12 34 leaves the value 12H in Register 34H sets the D flag and clears the C Z S V and H flags If Register 4BH contains...

Page 177: ...sing address mode ER for the source or destination specifies a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is infe...

Page 178: ...tains the value 1BH the statement SBCX 346H 129H Object Code 38 12 93 46 leaves the value 12H in Register 346H sets the D flag and clears the C Z S V and H flags If Register C6CH contains the value 2A...

Page 179: ...e Carry C flag is 1 regardless of its previous value Flags Attributes Example If the Carry flag is currently reset the statement SCF Object Code DF sets the Carry flag to 1 C Set to 1 Z Unaffected S U...

Page 180: ...If the destination address is prefixed by EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the o...

Page 181: ...t SRA R6 Object Code D0 E6 leaves the value 18H 00011000 in Working Register R6 sets the Carry flag and clears the Z V and S flags If Register C6 contains the value DFH and Register DFH contains the v...

Page 182: ...ddress is prefixed by EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Regis...

Page 183: ...ement SRL R6 Object Code 1F C0 E6 leaves the value 58H 01011000 in Working Register R6 sets the Carry flag and clears the Z V and S flags If Register C6 contains the value DFH and Register DFH contain...

Page 184: ...er Page Flags Attributes Example The statement SRP F0H Object Code 01 F0 sets the Register Pointer to access Working Register Group FH and Page 0H in the Register File All references to Working Regist...

Page 185: ...Z8 CPU into STOP mode Refer to the device specific Product Specification for details of STOP mode operation Flags Attributes Example The statements STOP Object Code 6F place the eZ8 CPU into STOP mode...

Page 186: ...r destination address is EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination operand in the opcode To access Re...

Page 187: ...ter 12H contains the value 1BH the statement SUB 34H 12H Object Code 24 12 34 leaves the value 13H in Register 34H sets the D flag and clears the C Z S V and H flags are cleared If Register 4BH contai...

Page 188: ...ing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is inferred For example the operand EE3H selects Working Register R3 The full 12 bit address is given by...

Page 189: ...ister 234H contains the value 2EH and Register 912H contains the value 1BH the statement SUBX 234H 912H Object Code 28 91 22 34 leaves the value 13H in Register 234H sets the D flag and clears the C Z...

Page 190: ...orking Register If the destination address is prefixed by EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination operand use ECH as the destination o...

Page 191: ...the statement SWAP BCH Object Code F0 BC leaves the value 3BH 00111011B in Register BCH and clears the Z and S flags If Working Register R5 contains the value BCH and Register BCH contains the value...

Page 192: ...their original values Flags Attributes Escaped Mode Addressing Using Escaped Mode Addressing address modes R or IR specify a Working Register If the high nibble of the source or destination address i...

Page 193: ...rking Register R0 contains the value 80H 10000000B testing bit 7 it is 1 the statement TCM D4H R0 Object Code 64 E0 D4 resets the Z flag because bit 7 in the destination operand is not a 1 sets the S...

Page 194: ...11 0904 eZ8 CPU Instruction Set Description eZ8 CPU User Manual 184 tests bit 4 of the Register A0H for 1 resets the Z flag indicating bit 4 in the destination operand was not 1 and clears the S and V...

Page 195: ...heir original values Flags Attributes Escaped Mode Addressing Using Escaped Mode Addressing address mode ER for the source or destination specifies a Working Register with 4 bit addressing If the high...

Page 196: ...1 the statement TCMX DD4H 420H Object Code 68 42 0D D4 resets the Z flag because bit 7 in the destination operand is not a 1 sets the S flag and clears the V flag If Register B52H contains the value...

Page 197: ...nal values Flags Attributes Escaped Mode Addressing Using Escaped Mode Addressing address modes R or IR specify a Working Register If the high nibble of the source or destination address is EH 1110B a...

Page 198: ...g and clears the V flag If Register D4H contains the value 08H 00001000B and Working Register R0 contains the value 04H 00000100B testing bit 2 if it is 0 the statement TM D4H R0 Object Code 74 E0 D4...

Page 199: ...189 If Register 5DH contains the value A0H and Register A0H contains the value 0FH 00001111B the statement TM 5D 10H Object Code 77 5D 10 tests bit 4 of the Register A0H for 0 sets the Z flag indicati...

Page 200: ...tributes Escaped Mode Addressing Using Escaped Mode Addressing address mode ER for the source or destination can spec ify a Working Register with 4 bit addressing If the high byte of the source or des...

Page 201: ...1 if it is 0 the statement TMX 789H 246H Object Code 78 24 67 89 sets the Z flag indicating bit 1 in the destination operand is 0 and clears the V and S flags If Register 13H contains the value F1H 11...

Page 202: ...IRET instruction to return from a trap There are 256 possible Trap Vector Pairs in Program Memory The Trap Vector Pairs are numbered from 0 to 255 The base addresses of the Trap Vector Pairs begin at...

Page 203: ...811 0904 eZ8 CPU Instruction Set Description eZ8 CPU User Manual 193 pushes the Flags and Program Counter onto the stack The Program Counter loads the value A02FH Program execution resumes at address...

Page 204: ...imer from timing out For more information on the Watch Dog Timer please refer to the relevant Product Specification for your part Flags Attributes Examples The first execution of the statement WDT Obj...

Page 205: ...IR specify a Working Register If the high nibble of the source or destination address is EH 1110B a Working Register is inferred For example if Working Register R12 CH is the desired destination oper...

Page 206: ...110101B and Register 42H contains the value 0AH 00001010B the statement XOR 3AH 42H Object Code B4 42 3A leaves the value FFH 11111111B in Register 3AH sets the S flag and clears the Z and V flags If...

Page 207: ...ce or destination specifies a Working Register with 4 bit addressing If the high byte of the source or destination address is EEH 11101110B a Working Regis ter is inferred For example the operand EE3H...

Page 208: ...ns the value 6AH 01101010 the statement XORX 93AH 142H Object Code B8 14 29 3A leaves the value 9FH 10011111B in Register 93AH sets the S flag and clears the Z and V flags If Register D7AH contains th...

Page 209: ...es opcode map cell description and Table 22 explains the abbreviations used in Figure 24 and 25 Figure 23 Opcode Map Cell Description CP 3 3 R2 R1 A 4 Opcode Lower Nibble Second Operand After Assembly...

Page 210: ...r 1 X 8 bit signed index or displacement r 4 bit Working Register DA Destination address R 8 bit register ER Extended Addressing register r1 R1 Ir1 Irr1 IR1 rr1 RR1 IRR1 ER1 Destination address IM Imm...

Page 211: ...3 4 IR1 IM ANDX 4 3 ER2 ER1 ANDX 4 3 IM ER1 COM 2 2 R1 COM 2 3 IR1 TCM 2 3 r1 r2 TCM 2 4 r1 Ir2 TCM 3 3 R2 R1 TCM 3 4 IR2 R1 TCM 3 3 R1 IM TCM 3 4 IR1 IM TCMX 4 3 ER2 ER1 TCMX 4 3 IM ER1 PUSH 2 2 R2...

Page 212: ...fter 1FH CPC 4 3 R2 R1 CPC 4 4 IR2 R1 CPC 3 3 r1 r2 CPC 3 4 r1 Ir2 CPCX 5 3 ER2 ER1 CPCX 5 3 IM ER1 CPC 4 3 R1 IM CPC 4 4 IR1 IM SRL 3 2 R1 SRL 3 3 IR1 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7...

Page 213: ...23 eZ8 CPU Instructions Sorted by Opcode Opcode s Hex Assembly Mnemonic Address Mode Flags Fetch Cycles Instr Cycles dst src C Z S V D H 00 BRK 1 2 01 SRP src IM 2 2 02 ADD dst src r r 0 2 3 03 ADD ds...

Page 214: ...NC dst r 1 2 1F70 PUSH src IM 3 2 1F A2 CPC dst src r r 3 3 1F A3 CPC dst src r Ir 3 4 1F A4 CPC dst src R R 4 3 1F A5 CPC dst src R IR 4 4 1F A6 CPC dst src R IM 4 3 1F A7 CPC dst src IR IM 4 4 1F A8...

Page 215: ...src r IM 2 2 2D JP LE dst DA 3 2 2E INC dst r 1 2 2F ATM 1 2 30 DEC dst R 2 2 31 DEC dst IR 2 3 32 SBC dst src r r 1 2 3 33 SBC dst src r Ir 1 2 4 34 SBC dst src R R 1 3 3 35 SBC dst src R IR 1 3 4 36...

Page 216: ...4 48 ORX dst src ER ER 0 4 3 49 ORX dst src ER IM 0 4 3 4A DJNZ dst RA r 2 3 4B JR OV dst DA 2 2 4C LD dst src r IM 2 2 4D JP OV dst DA 3 2 4E INC dst r 1 2 50 POP dst R 2 2 51 POP dst IR 2 3 52 AND...

Page 217: ...3 TCM dst src r Ir 0 2 4 64 TCM dst src R R 0 3 3 65 TCM dst src R IR 0 3 4 66 TCM dst src R IM 0 3 3 67 TCM dst src IR IM 0 3 4 68 TCMX dst src ER ER 0 4 3 69 TCMX dst src ER IM 0 4 3 6A DJNZ dst RA...

Page 218: ...c r IM 2 2 7D JP C dst DA 3 2 7E INC dst r 1 2 7F HALT 1 2 80 DECW dst RR 2 5 81 DECW dst IRR 2 6 82 LDE dst src r Irr 2 5 83 LDEI dst src Ir Irr 2 9 84 LDX dst src r ER 3 2 85 LDX dst src Ir ER 3 3 8...

Page 219: ...LDX dst src IRR IR 3 5 98 LEA dst X src r X r 3 3 99 LEA dst X src rr X rr 3 5 9A DJNZ dst RA r 2 3 9B JR GE dst DA 2 2 9C LD dst src r IM 2 2 9D JP GE dst DA 3 2 9E INC dst r 1 2 9F EI 1 2 A0 INCW d...

Page 220: ...B2 XOR dst src r r 0 2 3 B3 XOR dst src r Ir 0 2 4 B4 XOR dst src R R 0 3 3 B5 XOR dst src R IR 0 3 4 B6 XOR dst src R IM 0 3 3 B7 XOR dst src IR IM 0 3 4 B8 XORX dst src ER ER 0 4 3 B9 XORX dst src...

Page 221: ...2 2 CD JP NOV dst DA 3 2 CE INC dst r 1 2 CF RCF 0 1 2 D0 SRA dst R 0 2 2 D1 SRA dst IR 0 2 3 D2 LDC dst src Irr r 2 5 D3 LDCI dst src Irr Ir 2 9 D4 CALL dst IRR 2 6 D5 BSWAP dst R X 0 2 2 D6 CALL ds...

Page 222: ...E8 LDX dst src ER ER 4 2 E9 LDX dst src ER IM 4 2 EA DJNZ dst RA r 2 3 EB JR NZ dst DA 2 2 EC LD dst src r IM 2 2 ED JP NZ dst DA 3 2 EE INC dst r 1 2 EF CCF 1 2 F0 SWAP dst R X X 2 2 F1 SWAP dst IR X...

Page 223: ...dst RA r 2 3 FB JR NC dst DA 2 2 FC LD dst src r IM 2 2 FD JP NC dst DA 3 2 FE INC dst r 1 2 Table 23 eZ8 CPU Instructions Sorted by Opcode Opcode s Hex Assembly Mnemonic Address Mode Flags Fetch Cyc...

Page 224: ...Program Counter value The labels LABEL1 LABEL2 and LABEL3 are also assembly directives used to indicate addresses Table 24 Assembly and Object Code Example Program Counter Hex Object Code Hex Instruc...

Page 225: ...54 BSWAP 54 001053 LABEL1 001053 F6 27 FD BTJ 0 2 r7 LABEL1 001056 F6 B6 FA BTJ 1 3 r6 LABEL1 001059 F7 27 F7 BTJ 0 2 r7 LABEL1 00105C F7 B6 F4 BTJ 1 3 r6 LABEL1 00105F F7 B6 F1 BTJNZ 3 r6 LABEL1 001...

Page 226: ...32 CPC 37 32 00109F 1F A8 45 63 51 CPCX 351 456 0010A4 1F A9 35 03 64 CPCX 364 35 0010A9 A8 45 63 51 CPX 351 456 0010AD A9 35 03 64 CPX 364 35 0010B1 40 34 DA 34 0010B3 41 43 DA 43 0010B5 30 56 DEC 56...

Page 227: ...13 LABEL2 0010DA EA E2 DJNZ r14 LABEL2 0010DC FA E0 DJNZ r15 LABEL2 0010DE 9F EI 0010DF 7F HALT 0010E0 20 46 INC 46 0010E2 21 34 INC 34 0010E4 0E INC r0 0010E5 1E INC r1 0010E6 2E INC r2 0010E7 3E INC...

Page 228: ...515 001110 6D F6 16 JP Z F616 001113 7D F7 17 JP C F717 001116 8D F8 18 JP T F818 001119 9D F9 19 JP GE F919 00111C AD FA 1A JP GT FA1A 00111F BD FB 1B JP UGT FB1B 001122 CD FC 1C JP NOV FC1C 001125 D...

Page 229: ...C LABEL3 001150 LABEL3 001150 0C 30 LD r0 30 001152 1C 31 LD r1 31 001154 2C 32 LD r2 32 001156 3C 33 LD r3 33 001158 4C 34 LD r4 34 00115A 5C 35 LD r5 35 00115C 6C 36 LD r6 36 00115E 7C 37 LD r7 37 0...

Page 230: ...6 r8 001193 82 58 LDE r5 rr8 001195 92 52 LDE rr2 r5 001197 83 6A LDEI r6 rr10 001199 93 3E LDEI rr14 r3 00119B C7 16 E3 LD r1 E3 r6 00119E D7 68 10 LD 10 r8 r6 0011A1 E8 87 6E E3 LDX r3 876 0011A5 85...

Page 231: ...31 OR 36 31 0011DE 47 37 32 OR 37 32 0011E1 48 45 63 51 ORX 351 456 0011E5 49 35 03 64 ORX 364 35 0011E9 50 46 POP 46 0011EB 51 35 POP 35 0011ED D8 54 30 POPX 543 0011F0 70 54 PUSH 54 0011F2 71 34 PUS...

Page 232: ...A 67 001226 1F C0 41 SRL 41 001229 1F C1 67 SRL 67 00122C 01 35 SRP 35 00122E 6F STOP 00122F 22 57 SUB r5 r7 001231 23 68 SUB r6 r8 001233 24 55 34 SUB 34 55 001236 25 AA 35 SUB 35 AA 001239 26 36 31...

Page 233: ...AA 00126D 76 36 31 TM 36 31 001270 77 37 32 TM 37 32 001273 78 45 63 51 TMX 351 456 001277 79 35 03 64 TMX 364 35 00127B F2 35 TRAP 35 00127D 5F WDT 00127E B2 57 XOR r5 r7 001280 B3 68 XOR r6 r8 0012...

Page 234: ...ect code example 214 assembly language compatibility 9 source program example 35 syntax 36 B B 38 b 37 BCLR 39 big endian 8 binary number suffix symbol 38 BIT 39 70 72 bit addressing 17 clear 39 manip...

Page 235: ...cimal adjust instruction 39 decrement 101 and jump if non zero 106 instruction 39 jump non zero 42 word instruction 39 word DECW 103 DECW 39 destination operand symbol 38 DI 40 direct address notation...

Page 236: ...ANDX 41 66 68 arithmetic 38 39 BCLR 39 69 BIT 39 70 72 bit manipulation 38 39 block transfer 38 40 BRK 42 71 BSET 39 BSWAP 40 42 73 BTJ 75 BTJ 42 BTJNZ 42 78 BTJZ 42 81 CALL 42 84 CCF 40 86 CLR 41 87...

Page 237: ...enable and disable 30 example of vectoring in program memory 32 nesting of vectored interrupts 32 priority 30 software interrupt generation 33 vectored processing 30 IR 37 Ir 37 IRR 37 Irr 37 J JP cc...

Page 238: ...opcode 201 second map after 1FH 202 operands 35 operations 35 OR 41 143 using extended addressing 41 ORX 41 145 overflow flag 6 P p 37 page mode addressing 15 PC 38 polarity notation 37 polled interru...

Page 239: ...logical 42 172 sign flag 5 software trap 42 192 source operand symbol 38 source program 35 SP 38 SRA 42 170 src 38 SRL 42 172 SRP 40 174 stack pointer compatibility 12 high low byte 3 4 12 14 symbol 3...

Page 240: ...42 192 traps 34 U using extended addressing 39 V vector address notation 37 W watch dog timer 194 watch dog timer refresh 40 WDT 40 194 working register addressing 16 notation 37 pair notation 37 X X...

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