UM012811-0904
eZ8 CPU Instruction Set Description
eZ8 CPU
User Manual
95
CPCX
Compare with Carry using Extended Addressing
CPCX dst, src
Operation
dst - src - C
Description
The source operand with the C bit is compared to (subtracted from) the destination oper-
and and the appropriate flags are set accordingly. The contents of both operands are unaf-
fected. For multi-precision operation, repeating this instruction enables multi-byte
compares. Only if the initial state of the Zero flag is 1 and the result of the compare is 0 is
the Zero flag set.
Flags
Attributes
Escaped Mode Addressing
Using Escaped Mode Addressing, address mode ER for the source or destination can spec-
ify a Working Register with 4-bit addressing.
If the high byte of the source or destination address is
EEH
(11101110B), a Working Regis-
ter is inferred. For example, the operand
EE3H
selects Working Register R3. The full 12-
bit address is given by {RP[3:0], RP[7:4], 3H}.
To access Registers on Page EH (addresses
E00H
to
EFFH
), set the Page Pointer, RP[3:0],
to
EH
and set the Working Group Pointer, RP[7:4], to the desired Working Group.
C
Set if a borrow is required by bit 7; reset otherwise.
Z
Set if the result is zero and the initial Zero flag is 1; reset otherwise.
S
Set if the result is negative; reset otherwise.
V
Set if an arithmetic overflow occurs; reset otherwise.
D
Unaffected.
H
Unaffected.
Mnemonic Destination, Source
Opcode (Hex)
Operand 1
Operand 2
Operand 3
CPCX
ER1, ER2
1F A8
ER2[11:4]
{ER2[3:0], ER1[11:8]} ER1[7:0]
CPCX
ER1, IM
1F A9
IM
{0H, ER1[11:8]}
ER1[7:0]
