UM012811-0904
eZ8 CPU Instruction Set Description
eZ8 CPU
User Manual
176
SUB
Subtract
SUB dst, src
Operation
dst
←
dst - src
Description
This instruction subtracts the source operand from the destination operand. The destina-
tion operand stores the result. The source operand contents are unaffected. The eZ8 CPU
performs subtraction by adding the two’s complement of the source operand to the desti-
nation operand.
Flags
Attributes
Escaped Mode Addressing
Using Escaped Mode Addressing, address modes R or IR specify a Working Register. If
the high nibble of the source or destination address is
EH
(1110B), a Working Register is
inferred. For example, if Working Register R12 (
CH
) is the desired destination operand,
use
ECH
as the destination operand in the opcode. To access Registers with addresses
E0H
to
EFH
, either set the Working Group Pointer, RP[7:4], to
EH
or use indirect addressing.
C
Set if a borrow is required by bit 7; reset otherwise.
Z
Set if the result is zero; reset otherwise.
S
Set if the result is negative; reset otherwise.
V
Set if an arithmetic overflow occurs; reset otherwise.
D
Set to 1.
H
Set if a borrow is required by bit 3; reset otherwise.
Mnemonic
Destination, Source
Opcode (Hex)
Operand 1
Operand 2
Operand 3
SUB
r1, r2
22
{r1, r2}
—
—
SUB
r1, @r2
23
{r1, r2}
—
—
SUB
R1, R2
24
R2
R1
—
SUB
R1, @R2
25
R2
R1
—
SUB
R1, IM
26
R1
IM
—
SUB
@R1, IM
27
R1
IM
—
