eZ8 CPU
User Manual
UM012811-0904
Opcodes Listed Numerically
203
Opcodes Listed Numerically
Table 23 lists the eZ8 CPU instructions, sorted numerically by the opcode. The table iden-
tifies the addressing modes employed by the instruction, the effect upon the Flags register,
the number of CPU clock cycles required for the instruction fetch, and the number of CPU
clock cycles required for the instruction execution.
.
Table 23. eZ8 CPU Instructions Sorted by Opcode
Opcode(s)
(Hex)
Assembly Mnemonic
Address Mode
Flags
Fetch
Cycles
Instr.
Cycles
dst
src
C
Z
S
V
D
H
00
BRK
-
-
-
-
-
-
1
2
01
SRP src
IM
-
-
-
-
-
-
2
2
02
ADD dst, src
r
r
*
*
*
*
0
*
2
3
03
ADD dst, src
r
Ir
*
*
*
*
0
*
2
4
04
ADD dst, src
R
R
*
*
*
*
0
*
3
3
05
ADD dst, src
R
IR
*
*
*
*
0
*
3
4
06
ADD dst, src
R
IM
*
*
*
*
0
*
3
3
07
ADD dst, src
IR
IM
*
*
*
*
0
*
3
4
08
ADDX dst, src
ER
ER
*
*
*
*
0
*
4
3
09
ADDX dst, src
ER
IM
*
*
*
*
0
*
4
3
0A
DJNZ dst, RA
r
-
-
-
-
-
-
2
3
0B
JR F, dst
DA
-
-
-
-
-
-
2
2
0C
LD dst, src
r
IM
-
-
-
-
-
-
2
2
0D
JP F, dst
DA
-
-
-
-
-
-
3
2
0E
INC dst
r
-
*
*
*
-
-
1
2
0F
NOP
-
-
-
-
-
-
1
2
10
RLC dst
R
*
*
*
*
-
-
2
2
Flags Notation: * = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
