UM012811-0904
eZ8 CPU Instruction Set Description
eZ8 CPU
User Manual
57
ADCX
Add with Carry using Extended Addressing
ADCX dst, src
Operation
dst
←
dst + src + C
Description
Add the source operand and the Carry (C) flag to the destination operand. Perform two’s-
complement addition. Store the sum in the destination operand. The contents of the source
operand are not affected. In multiple-precision (multi-byte) arithmetic, this instruction
permits the carry from the addition of low-order byte operations to be carried into the
addition of high-order bytes. The destination and source operands use 12-bit addresses to
access any address in the Register File.
Flags
Attributes
Escaped Mode Addressing
Using Escaped Mode Addressing, address mode ER for the source or destination can spec-
ify a Working Register with 4-bit addressing.
If the high byte of the source or destination address is
EEH
(11101110B), a Working Regis-
ter is inferred. For example, the operand
EE3H
selects Working Register R3. The full 12-
bit address is given by {RP[3:0], RP[7:4], 3H}.
To access Registers on Page EH (addresses
E00H
to
EFFH
), set the Page Pointer, RP[3:0],
to
EH
and set the Working Group Pointer, RP[7:4], to the desired Working Group.
C
Set if there is a carry from bit 7; reset otherwise.
Z
Set if the result is zero; reset otherwise.
S
Set if the result is negative; reset otherwise.
V
Set if an arithmetic overflow occurs; reset otherwise.
D
Reset to 0.
H
Set if there is a carry from bit 3 of the result; reset otherwise.
Mnemonic Destination, Source
Opcode (Hex)
Operand 1
Operand 2
Operand 3
ADCX
ER1, ER2
18
ER2[11:4]
{ER2[3:0], ER1[11:8]} ER1[7:0]
ADCX
ER1, IM
19
IM
{0H, ER1[11:8]}
ER1[7:0]
