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2. Interface Operation

56

Tsi308 User Manual

80D4000_MA001_02

Tundra Semiconductor Corporation

www.tundra.com

2.10.3.3

 PCI Parity Errors

All PCI devices are required to drive even parity on P_PAR when they are driving the bottom 
half of the P_AD bus, and on P_PAR64 when they are driving the top half.

The Tsi301 checks parity on the P_AD bus during command/address phases and data phases 
when it receives data. The Tsi308 then logs bad parity in the DetParErr bit of the Secondary Bus 
Status CSR. Other action is taken only if enabled by the ParErrRespEn bit in the Bridge Control 
CSR. The action taken depends on the type of information being transferred at the time of the 
error and in which direction the transfer was occurring.

Table 10

 indicates the CSR bits used to log and enable reporting of each PCI parity error.

The Tsi308 may also sample P_PERR_N, asserted when it is driving write data out, indicating 
that a parity error was detected by the target of the write. If the ParErrRespEn bit is set and the 
request was a non-posted write, it receives an error response. If the request was a posted write 
and the PostFatalEn or NonPostFatalEn bits in the Error Control CSR are enabled, the error is 
signaled by one of the error interrupts.

2.11

 Test Features

 

The following test features are included in the Tsi308 to facilitate testing of the chip.

2.11.1

 JTAG

 

The Tsi308s’s JTAG interface is compliant to IEEE 1149.1 standard. The basic test operation is 

controlled through five pins namely TCK, TMS, TDI, TDO and TRST_N. In Tsi308, JTAG 
interface is used for Memory BIST, JTAG CSR Read/Write, Force Tri-state, Boundary Scan and 
Core clock frequency selection during BIST.

Table 10: PCI Parity Errors CSR Bits

Error in

Fatal Interrupt

NonFatal Interrupt

PCI

Command/Address

Error/ CmdPerrFatalEn

Error/ CmdPerrNonFatalEn

If decode has caused the 

Tsi308 to drive 

P_DEVSEL_N, Target Abort 

Write Data to Tsi308

Not Supported

Not Supported

Assert P_PERR_N

Read Data to Tsi308

Not Supported

Not Supported

Set SecStatus/ MstrDParErr, 

return HyperTransport error 

response,

and assert P_PERR_N

Summary of Contents for TSI308

Page 1: ...Tundra Semiconductor Corporation TitlePage 80D4000_MA001_02 Tsi308 HyperTransport to PCI X Bridge User Manual Document Number 80D4000_MA001_02 Document Status Preliminary Revision Date September 2006 ...

Page 2: ...able Canadian or other legislation is hereby expressly prohibited User obtains no rights in the information or in any product process technology or trademark which it includes or describes and is expressly prohibited from modifying the information or creating derivative works without the express written consent of Tundra Disclaimer Tundra assumes no responsibility for the accuracy or completeness ...

Page 3: ...3 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com Contact Information Text inset to be placed ...

Page 4: ...4 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 5: ...5 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com Corporate Profile Text inset to be inserted later ...

Page 6: ...6 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 7: ...face 25 1 4 1 PCI X Master 25 1 4 2 PCI X Slave 26 1 4 3 PCI X Arbiter 26 1 5 Interrupt Controller 27 1 6 Interface Levels 27 1 7 Clocking 28 1 8 Reset 28 2 Interface Operation 29 2 2 HyperTransport Interface 31 2 2 1 HyperTransport Packet Reception 32 2 2 2 HyperTransport Address Map 35 2 2 3 HyperTransport Address Remap 37 2 2 4 HyperTransport Packet Transmission 37 2 3 Outbound Transactions 38 ...

Page 8: ...t 47 2 9 3 Reset Configuration 47 2 9 4 HyperTransport Link Initialization 47 2 9 5 HyperTransport Fabric Initialization 48 2 9 6 Secondary Bus Reset 49 2 10 Error Handling 49 2 10 1 Reporting 49 2 10 2 HyperTransport Errors 50 2 10 3 PCI Errors 53 2 11 Test Features 56 2 11 1 JTAG 56 2 11 2 SCAN and ATPG 68 3 Clock Frequency and Mode Selection Hardware Straps 71 3 1 Overview 71 3 2 Core Clock Fre...

Page 9: ...ters 97 4 3 6 CSR Layout for IOAPIC 181 4 3 7 IOAPIC Registers 183 5 Electrical Characteristics 189 5 1 AC Timing Definitions 190 5 1 1 AC Timing Values 191 5 2 Clock Parameters 193 5 2 1 Input Clock 193 5 3 HyperTransport Output Timing Characteristics 194 5 3 1 Differential Output Skew 194 5 3 2 TCADV TCADValid 195 5 4 HyperTransport Input Timing Characteristics 196 5 4 1 Input Differential Skew ...

Page 10: ...9 7 2 Insertion and Removal Sequence 239 8 Typical Applications 241 8 1 Recommendations for Use 241 8 1 1 Unused HyperTransport CAD CLK and CTL Inputs 241 8 1 2 Analog PLL Power Filtering 242 8 1 3 Decoupling Capacitor Recommendations 243 8 2 PCB Layout Guidelines 243 8 2 1 Tsi308 HyperTransport Interface Layout Guidelines 243 8 2 2 Layout Guidelines 246 8 2 3 AS90L10208 Board Trace Electrical Spe...

Page 11: ...Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com Contents 11 9 Ordering Information 257 Index 259 ...

Page 12: ...Contents 12 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 13: ...Figure 8 Tsi308 Dual PCI X Mode 84 Figure 9 Timing Definitions Waveform 190 Figure 10 Input Clock Parameters Waveform 193 Figure 11 TODIFF 194 Figure 12 TCADV 195 Figure 13 TIDIFF 196 Figure 14 TSU and THD 197 Figure 15 TCADVRS TCADVRH 198 Figure 16 Output Loading for AC Timing 202 Figure 17 Output Reference System Load 203 Figure 18 Tsi308 Reset Timing 205 Figure 19 Recommended Heat Sink for Tsi3...

Page 14: ...List of Figures 14 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 15: ...cy Selection Straps in RevC mode 74 Table 15 PCI B Clock Frequency Selection Straps 74 Table 16 P0_CLK and CoreClock Frequency Selection Straps 75 Table 17 P1_CLK Frequency Selection Straps 76 Table 18 Link Transmit Clock Frequency Selection Straps 76 Table 19 Miscellaneous Pin Straps 78 Table 20 Tsi308 CSR Header 86 Table 21 64 bit Address Remap Indexed Registers 89 Table 22 Interrupt Definition ...

Page 16: ...mber 221 Table 37 Tsi308 Multiplexed Pins 232 Table 38 Tsi308 1 2V HyperTransport Power 232 Table 39 Tsi308 1 8V Core Power 233 Table 40 Tsi308 1 8V Analog PLL Power and Ground 234 Table 41 Tsi308 3 3V PCI Core and I O Power and HT Receive Power 234 Table 42 Tsi308 Ground Pins 236 Table 43 System Board Design Rules 247 Table 44 Pad to Ball Trace Length Information 252 Table 45 Ordering Information...

Page 17: ...ications with these devices Document Conventions This document uses a variety of conventions to establish consistency and to help you quickly locate information of interest These conventions are briefly discussed in the following sections Non differential Signal Notation Non differential signals are either active low or active high An active low signal has an active state of logic 0 or the lower v...

Page 18: ...numbers are denoted by the prefix 0x For example 0x04 Binary numbers are denoted by the prefix 0b For example 0b010 Registers that have multiple iterations are denoted by x y in their names where x is first register and address and y is the last register and address For example REG 0 3 indicates there are four versions of the register at different addresses REG0 REG1 REG2 and REG3 Symbols State Si...

Page 19: ...oduct that is near production ready and is revised as required Final Contains information about a final customer ready product and is available once the product is released to production Related Information The following documents contain useful reference information for using this manual Tsi384 Hardware Manual Tsi384 Software Initialization Application Note Tsi384 Device Errata and Design Notes T...

Page 20: ...20 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 21: ...m 1 Functional Description This chapter discusses the following topics about the Tsi308 Overview on page 22 Features on page 23 HyperTransport Interface on page 24 PCI X Interface on page 25 Interrupt Controller on page 27 Interface Levels on page 27 Clocking on page 28 Reset on page 28 ...

Page 22: ...acity systems with multiple PCI X busses and HT based peripherals A fairness algorithm allocates bandwidth among devices thereby eliminating starvation of bridges at the end of the chain The Tsi308 breathes new life into systems that are encumbered by the limits of traditional PCI or PCI X based fabrics It reduces the time to market design complexity and system costs of PCI X and HT based systems ...

Page 23: ...vices with virtual internal tunnel in dual PCI X mode Implements two independent sets of CSRs in dual PCI X mode PCI X bus can also operate in traditional PCI mode Operating frequencies and mode of the two PCI X buses are independently selectable Supports 50 66 100 and 133 MHZ in PCI X mode Supports 25 33 50 and 66 MHZ in PCI mode PCI X mode complies to Revision 1 0b of PCI X Addendum to the PCI L...

Page 24: ...ating at 25 or 33 MHZ 388 pin HSBGA package Compatible with x86 systems Supports Online Insertion and Removal Supports Boundary scan Software and Hardware compatibility Revision A Revision B 1 3 HyperTransport Interface The Tsi308 HyperTransport to PCI X bridge primary interface is a HyperTransport tunnel The primary interface is compliant with HyperTransport I O Link Specification Revision 1 05 T...

Page 25: ...rted The Tsi308 supports the full 64 bit memory mapped space and 25 bit I O space described in HyperTransport I O Link Specification Revision 1 05 In addition device supports 64 bit address remapping capability and a single upstream DMA window PCI dual address cycle DAC support is provided both inbound and outbound to support memory mapped space The Tsi308 supports configuration accesses to device...

Page 26: ... back to back transactions are supported Prefetching is supported for all flavors of memory read cycle while operating in standard PCI mode which separate prefetch controls for each cycle type and a maximum prefetch per read of 512 bytes Prefetching may be done once at the beginning of each read or it may be enabled to continuously issue requests as data is drained to PCI All prefetch data is disc...

Page 27: ... to previous generation Tsi301 chip Tsi308 also implements an alternate register map to program the interrupts in a non standard way However these registers are visible to software only when Tsi308 is operating in Tsi301 software compatible mode by hardware strap settings and this is the only means to program interrupts in Tsi301 mode 1 6 Interface Levels A complete pinout of the Tsi308 is provide...

Page 28: ...ound in 3 Though three pins above indicate operating mode PCI or PCI X and frequency group 33MHz or 66 MHz or 133 MHz Tsi308 needs exact operating frequency of a given bus to generate internal clocks as well as to generate PCI X Initialization Pattern for devices on PCI X bus as specified in 3 This is done through hardware straps These straps are sampled using combinational logic while warm cold r...

Page 29: ... 29 HyperTransport Interface on page 31 Outbound Transactions on page 38 Inbound Transactions on page 40 PCI X Arbiter on page 45 Online Insertion and Removal OIR on page 46 LDTSTOP Support on page 46 Power Management on page 47 Reset on page 47 Error Handling on page 49 Test Features on page 56 2 1 Overview This chapter details the operation of the HyperTransport to PCI X Bridge chip ...

Page 30: ...4 Entries Data Mover Rx Data RAM 24 Entries Rx Cmd Buffers 24 Entries Rx Data RAM 24 Entries Rx Cmd Buffers 24 Entries Data Mover Rx Data RAM 24 Entries Rx Cmd Buffers 24 Entries Rx Data RAM 24 Entries PCI X Resp Buffer 16 X 64 Outbound ReqCtl 16 X 64 DelReqBuf 4 Req entries PReqBuf RAM 128 X 64 PCI X Target PReqBuf RAM 128 X 64 DelReqBuf 4 Req entries Outbound Data RAM 256 X 64 PCI X Resp Buffer ...

Page 31: ...destination which accepts the packet Link interfaces in the Tsi308 are symmetrical which allows connection to either bridge link toward a host The Tsi308 also supports being placed in a double hosted chain with hosts on both ends Figure 3 Single HyperTransport Link Interface Block Diagram HT Receive PHY HT Transmit PHY Rx Sync FIFO Tx Sync FIFO Flood Generator Packet Framing Command Address Decode...

Page 32: ...artitioned among the three virtual channels posted non posted and response with each channel allocated space to hold eight commands and eight data packets However packets originated on PCI X bus is locally buffered in respective PCI X Ports and delivered directly to the appropriate HT Link HT Receive PHY HT Transmit PHY Rx Sync FIFO Tx Sync FIFO Flood Generator Packet Framing Command Address Decod...

Page 33: ... packets are always forwarded toward the host and are never accepted by the Tsi308 chip Downstream RdSized and WrSized request packet addresses are decoded according to the HyperTransport Address Map described in Section 3 3 and are accepted if they match any Tsi308 address ranges of any PCI X ports or internal CSRs Downstream WrSized and RdSized that do not match any of the Tsi308 address ranges ...

Page 34: ...eiving link Tsi308 implements a proprietary control bit StoreForward per link in its CSR which system software can program that tells the Tsi308 whether to stream low latency or not It is the Rx Command Buffer s responsibility to ensure that required packet ordering is maintained so packets can be committed as soon as they are passed to the link controller Packets that do not have any ordering req...

Page 35: ...rTransport are mapped into this space The Tsi308 checks addresses on incoming packets in each space for ranges that it accepts Table 3 PCI Bus Transaction Ordering Row Pass Column Posted Memory Write PMW Delayed Read Request DRR Delayed Write Request DWR Delayed Read Completion DRC Delayed Write Completion DWC PMW No Yes Yes Yes Yes DRR No No No No No DWR No No No No No DRC No Yes Yes No No DWC No...

Page 36: ... address range of 0000_00FD_FC00_0000h to 0000_00FD_FDFF_FFFFh The Tsi308 strips the top 39 bits off of the addresses in this range If enabled by I OspaceEn in the Cmd CSR the Tsi308 accepts requests that fall in the range defined by the I O Base and I O Range Base Upper and I O Limit and I O Range Limit Upper CSRs If set the IsaEn bit in Bridge Control CSR creates a series of holes the top 768 by...

Page 37: ...bone for I O systems which are likely to contain a variety of other buses with varying addressing capabilities the HyperTransport specification defines mechanism to remap the HyperTransport addresses to locally defined addresses of other buses allowing mapping of the smaller address spaces of individual buses into different locations within the HyperTransport technology address map To support this...

Page 38: ...mit Control CSR 6Eh to prevent them from occupying too much bandwidth in a busy stream Throttling buffer releases clumps the released messages together and raises their efficiency In a single hosted HyperTransport chain the Tsi308 may be at the end of the chain furthest from the host and therefore have no downstream link connection In this case packets are routed to the End of Chain EOC logic in t...

Page 39: ...n posted the transaction will require generation of a response to the host ORC considers posted transactions as complete when the request completes at its destination and the buffer is retired Non posted transactions are complete when the response packet is issued to the HyperTransport transmit interface from which the request was received 2 3 1 PCI X Outbound Transactions Outbound requests to PCI...

Page 40: ...equest is non posted the transaction also includes the response from the host bridge back to the original requesting unit The Tsi308 operates as a PCI X target for requests from external PCI X devices All accepted requests are forwarded to the HyperTransport link interface leading to the host Reads go through the delayed request buffers and are handled on the PCI X bus as delayed requests when in ...

Page 41: ...are posted to the HyperTransport chain except I O writes which is non posted The Tsi308 never responds to Configuration Writes A total of 1024 bytes of buffering for posted data is provided per PCI X bus Memory Write and Memory Write Invalidate commands stream data into the chip disconnecting either on 4 KB boundaries or when all of the internal buffer space is filled The Tsi308 generates the larg...

Page 42: ...rTransport requests Transactions for which prefetching is enabled issue a HyperTransport read for the remainder of the 64 byte aligned block containing the original request These transactions also issue HyperTransport reads for the zero to seven complete 64 byte blocks following as determined by the Read Control CSRs The total number of reads that may be outstanding to HyperTransport at one time i...

Page 43: ...ing nonzero SeqID to guarantee ordering at the target This 4 bit SeqID is formed by concatenating a leading 1 guaranteeing a nonzero result with the 2 bit delayed request buffer number and one bit that toggles for each occupation of the delayed request buffer The concatenation prevents consecutive PCI X reads from being issued with the same SeqID and appearing to have HyperTransport ordering requi...

Page 44: ...ffer four 512 byte entries for the accumulation of read response data to return to the PCI X bus These four buffers correspond to four read requests in Delayed Request Buffers Data returning from HyperTransport is loaded into the buffer based on the comparison between request information stored in the corresponding delayed request number and information contained in response header and drained out...

Page 45: ...ay be observed by monitoring the Active field of the same CSR 2 5 PCI X Arbiter The Tsi308 includes a PCI X arbiter for each PCI X port The arbiter is an independent unit The Tsi308 s internal PCI X request and PCI X grant signals are connected to pins as Px_REQ_OUT_N and Px_GNT_IN_N x 0 for PCI A and x 1 for PCI B It is possible to either use this arbiter or to bypass it and use an external arbit...

Page 46: ...ct NOP packets through the end of current CRC window and continuing through the transmission of the CRC bits for the current window the transmitter continues to drive disconnect NOP packets on the link for 64 bit times after which point transmitter waits for the corresponding receiver on the same link to complete its disconnect sequence and then disables its drives if LDTSTOP tri state enable bit ...

Page 47: ...the loading of internal registers from strapped PCI bus pins and the SRI Serial ROM Interface The PCI X bus is held in reset until the deassertion of L_RST_N 2 9 2 Warm Reset Warm reset of the Tsi308 is caused by the assertion of L_RST_N while leaving L_POWER_OK asserted Once asserted L_RST_N must remain asserted for at least 1 ms Warm reset results in the initialization of most internal state wit...

Page 48: ...ice number 0 is accepted by the first uninitialized device on the chain This is the device at the far end of the link currently being sized 3 Performing a write to the HyperTransport Command register without changing any fields causes initialization of the master host bit This indicates the HyperTransport link that connects toward the host bridge Polling the error bits for that link determines whe...

Page 49: ...d control routing of error notification Not all signaling methods are available for all error types When the Tsi308 takes an error it signals the system in one of three ways The error signaling methods are listed below in order of increasing severity For errors detected by the Tsi308 as a transaction target errors may be signaled in the bridge chip response The method of signaling in the response ...

Page 50: ...s are lost This option is only available for catastrophic HyperTransport errors that render the chain untrustworthy Any error that causes sync flooding also sets the LinkFail bit in the HyperTransport Link 0 1 Control CSR for the link on which the error was detected The setting of LinkFail will cause that link to not be re initialized on the next warm reset event The SigdSerr bit in the Status CSR...

Page 51: ...broadcast it is silently dropped it has traversed the whole chain 3 If the outgoing packet was not a non posted request either posted request or response or a broadcast then there is no in band way to signal the error The packet is dropped and may be signaled as an error as shown in Table 6 Tsi308 supports Drop on Uninitialized Link if this bit is set then a transmitter with its Initialization com...

Page 52: ...contain an error assertion indicated by the Error bit In this case the NXA bit indicates whether the error was caused by the access failing to reach a target value of 1 or signaled by the target value of 0 An NXA bit value of 1 is roughly equivalent to a PCI master abort An NXA bit value of 0 is equivalent to a PCI target abort In general these errors are signaled to the PCI bus in the same way as...

Page 53: ...nses equivalent to a PCI target abort No other action is taken Error responses may also be signaled to HyperTransport because of errors taken when the request was issued to PCI 2 10 3 PCI Errors 2 10 3 1 PCI System Errors PCI devices may assert an unrecoverable system error by asserting SERR on the secondary PCI bus Table 7 HyperTransport Master Errors CSR Bits Error Log Bit Fatal Interrupt NonFat...

Page 54: ...PCI requests issued are forwarded through the Tsi308 from HyperTransport If the HyperTransport request was non posted error status may be returned to the HyperTransport requester in the response If it was posted the error may only be signaled by the error interrupts A single set of error reporting controls is used for all posted requests regardless of the specific error taken Table 8 PCI System Er...

Page 55: ...n Error response If Error PostFatalEn 1 assert FATAL_ERR_N If Error PostNonFatalEn 1 assert NONFATAL_ERR_N TRDY Timeout Not supported Return Error response If Error PostFatalEn 1 assert FATAL_ERR_N If Error PostNonFatalEn 1 assert NONFATAL_ERR_N Retry Timeout Error RetryTimeout Return Error response If Error PostFatalEn 1 assert FATAL_ERR_N If Error PostNonFatalEn 1 assert NONFATAL_ERR_N Table 9 P...

Page 56: ...detected by the target of the write If the ParErrRespEn bit is set and the request was a non posted write it receives an error response If the request was a posted write and the PostFatalEn or NonPostFatalEn bits in the Error Control CSR are enabled the error is signaled by one of the error interrupts 2 11 Test Features The following test features are included in the Tsi308 to facilitate testing o...

Page 57: ...gnals are needed to control the test activity of the chip instead of the ad hoc Bed of Nails technique Boundary Scan JTAG instruction SAMPLE PRELOAD access the boundary scan register via a data scan operation to take a sample of the functional data entering and leaving the device This instruction is also used to preload test data into the boundary scan register prior to loading and EXTEST instruct...

Page 58: ... TX_BYPASS_CLK_E input 2 bc_7 PLL_SEL_BK bidir 3 3 bc_1 control 4 bc_7 PLL_SELDIV2 bidir 5 5 bc_1 control 6 bc_4 L0_TX_BYPASS_CLK input 7 bc_1 L0_DCLK_TEST output3 8 8 bc_1 control 9 bc_1 internal 10 bc_1 internal 11 bc_7 P1_TSTDIO bidir 12 12 bc_1 control 13 bc_1 P0_TSTCLK output3 14 14 bc_1 control 15 bc_1 P0_TSTDI output3 16 16 bc_1 control 17 bc_7 P0_TSTDIO bidir 18 18 bc_1 control 19 bc_4 P0_...

Page 59: ..._OIR_DISCON_EVENT input 34 bc_4 REFCLK_C_I input 35 bc_4 P0_CLK input 36 bc_7 P0_AD0 bidir 37 37 bc_1 control 38 bc_7 P0_AD1 bidir 37 39 bc_7 P0_AD2 bidir 40 40 bc_1 control 41 bc_7 P0_AD3 bidir 40 42 bc_7 P0_AD4 bidir 43 43 bc_1 control 44 bc_7 P0_AD5 bidir 43 45 bc_7 P0_AD6 bidir 46 46 bc_1 control 47 bc_7 P0_AD7 bidir 46 48 bc_7 P0_AD8 bidir 49 49 bc_1 control 50 bc_7 P0_AD9 bidir 49 51 bc_7 P0...

Page 60: ... P0_AD16 bidir 61 61 bc_1 control 62 bc_7 P0_AD17 bidir 61 63 bc_7 P0_AD18 bidir 64 64 bc_1 control 65 bc_7 P0_AD19 bidir 64 66 bc_7 P0_AD20 bidir 67 67 bc_1 control 68 bc_7 P0_AD21 bidir 67 69 bc_7 P0_AD22 bidir 70 70 bc_1 control 71 bc_7 P0_AD23 bidir 70 72 bc_7 P0_AD24 bidir 73 73 bc_1 control 74 bc_7 P0_AD25 bidir 73 75 bc_7 P0_AD26 bidir 76 76 bc_1 control 77 bc_7 P0_AD27 bidir 76 78 bc_7 P0_...

Page 61: ...P0_CBE2_N bidir 88 88 bc_1 control 89 bc_7 P0_CBE3_N bidir 88 90 bc_7 P0_DEVSEL_N bidir 91 91 bc_1 control 92 bc_7 P0_FRAME_N bidir 93 93 bc_1 control 94 bc_7 P0_IRDY_N bidir 95 95 bc_1 control 96 bc_7 P0_TRDY_N bidir 97 97 bc_1 control 98 bc_7 P0_STOP_N bidir 99 99 bc_1 control 100 bc_7 P0_LOCK_N bidir 101 101 bc_1 control 102 bc_7 P0_SERR_N bidir 103 103 bc_1 control 104 bc_7 P0_PERR_N bidir 105...

Page 62: ... bc_4 P0_REQ1_N input 116 bc_4 P0_REQ2_N input 117 bc_4 P0_REQ3_N input 118 bc_4 P0_REQ4_N input 119 bc_4 P0_REQ5_N input 120 bc_1 P0_GNT0_N output3 121 121 bc_1 control 122 bc_1 P0_GNT1_N output3 123 123 bc_1 control 124 bc_1 P0_GNT2_N output3 125 125 bc_1 control 126 bc_1 P0_GNT3_N output3 127 127 bc_1 control 128 bc_1 P0_GNT4_N output3 129 129 bc_1 control 130 bc_1 P0_GNT5_N output3 131 131 bc_...

Page 63: ..._IRQ4 input 143 bc_4 P0_BLK0_IRQ4 input 144 bc_4 P0_BLK0_IRQ0 input 145 bc_4 P0_BLK0_IRQ1 input 146 bc_4 P0_BLK0_IRQ2 input 147 bc_4 P0_BLK0_IRQ3 input 148 bc_4 L1_TX_BYPASS_CLK input 149 bc_1 L1_DCLK_TEST output3 150 150 bc_1 control 151 bc_1 L1_CCLK_TEST output3 152 152 bc_1 control 153 bc_4 P1_M66EN input 154 bc_4 P1_PCIX_N input 155 bc_4 P1_PCIX_133_N input 156 bc_4 P1_OIR_DISCON_EVENT input 1...

Page 64: ...TEST output3 168 168 bc_1 control 169 bc_1 P1_RST_N output3 170 170 bc_1 control 171 bc_4 P1_CLK input 172 bc_7 P1_AD0 bidir 173 173 bc_1 control 174 bc_7 P1_AD1 bidir 173 175 bc_7 P1_AD2 bidir 176 176 bc_1 control 177 bc_7 P1_AD3 bidir 176 178 bc_7 P1_AD4 bidir 179 179 bc_1 control 180 bc_7 P1_AD5 bidir 179 181 bc_7 P1_AD6 bidir 182 182 bc_1 control 183 bc_7 P1_AD7 bidir 182 184 bc_7 P1_AD8 bidir...

Page 65: ...bidir 194 196 bc_7 P1_AD16 bidir 197 197 bc_1 control 198 bc_7 P1_AD17 bidir 197 199 bc_7 P1_AD18 bidir 200 200 bc_1 control 201 bc_7 P1_AD19 bidir 200 202 bc_7 P1_AD20 bidir 203 203 bc_1 control 204 bc_7 P1_AD21 bidir 203 205 bc_7 P1_AD22 bidir 206 206 bc_1 control 207 bc_7 P1_AD23 bidir 206 208 bc_7 P1_AD24 bidir 209 209 bc_1 control 210 bc_7 P1_AD25 bidir 209 211 bc_7 P1_AD26 bidir 212 212 bc_1...

Page 66: ... bidir 221 223 bc_7 P1_CBE2_N bidir 224 224 bc_1 control 225 bc_7 P1_CBE3_N bidir 224 226 bc_7 P1_DEVSEL_N bidir 227 227 bc_1 control 228 bc_7 P1_FRAME_N bidir 229 229 bc_1 control 230 bc_7 P1_IRDY_N bidir 231 231 bc_1 control 232 bc_7 P1_TRDY_N bidir 233 233 bc_1 control 234 bc_7 P1_STOP_N bidir 235 235 bc_1 control 236 bc_7 P1_LOCK_N bidir 237 237 bc_1 control 238 bc_7 P1_SERR_N bidir 239 239 bc...

Page 67: ...REQ5_N input 250 bc_1 P1_GNT0_N output3 251 251 bc_1 control 252 bc_1 P1_GNT1_N output3 253 253 bc_1 control 254 bc_1 P1_GNT2_N output3 255 255 bc_1 control 256 bc_1 P1_GNT3_N output3 257 257 bc_1 control 258 bc_1 P1_GNT4_N output3 259 259 bc_1 control 260 bc_1 P1_GNT5_N output3 261 261 bc_1 control 262 bc_1 P1_REQ_OUT_N output3 263 263 bc_1 control 264 bc_4 P1_GNT_IN_N input 265 bc_4 L_POWER_OK i...

Page 68: ...t and output pins onto functional pins Table 12 Scan Input and Output Pins Chain Number Scan Input Scan Output 1 P0_BLK1_IRQ4 P1_AD0 2 P0_BLK0_IRQ4 P1_AD1 3 P0_BLK1_IRQ3 P1_AD2 4 P0_BLK1_IRQ2 P1_AD3 5 P0_BLK1_IRQ1 P1_AD4 6 P0_BLK1_IRQ0 P1_AD5 7 P0_BLK0_IRQ3 P1_AD6 8 P0_BLK0_IRQ2 P1_AD7 9 P0_BLK0_IRQ1 P1_AD8 10 P0_BLK0_IRQ0 P1_AD9 11 P1_BLK1_IRQ4 P1_AD10 12 P1_BLK0_IRQ4 P1_AD11 13 P1_BLK1_IRQ3 P1_A...

Page 69: ...2 Interface Operation 69 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 70: ...2 Interface Operation 70 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 71: ...five PLLs HT0_PLL_0 HT1_PLL_1 CORE_PLL PCI_A_PLL and PCI_B_PLL The reference clock for the first three PLLs is REFCLK_C in RevC mode and P0_CLK in non RevC mode The reference clock for PCI_A_PLL is P0_CLK and the reference clock for PCI_B_PLL is P1_CLK HT0_PLL generates the HyperTransport transmit clock for Link 0 HT1_PLL generates the HyperTransport transmit clock for Link 1 CORE_PLL generates th...

Page 72: ...must be derived from the same base frequency source If not asynchronous link initialization must be used No phase relationship is required in either mode When operating in RevC mode Tsi308 derives core clock from REFCLK_C RevC mode is set through hardware strap option A CORE PLL is used to generate core clock REFCLK_C is also fed to internal PLLs that generate HyperTransport transmit clocks for bo...

Page 73: ... and runs directly at P0_CLK at other modes Following sections describe the strap options 3 2 Core Clock Frequency Selection in RevC mode All the inputs to Core PLL are taken from the straps These strap values are taken during cold reset period Table 13 shows the valid strap combinations for Core PLL For all the straps that use P0_AD bus logic 1 assumes that the signal is pulled high to 3 3v suppl...

Page 74: ...p combinations for PCI A PLL Table 14 PCI A Clock Frequency Selection Straps in RevC mode P0_133_N P0_PCIX_N P0_M66EN MODE P0_AD 6 PCI_CLK_A MHz 1 1 0 PCI 1 25 1 1 0 PCI 0 33 1 1 1 PCI 1 50 1 1 1 PCI 0 66 1 0 N A PCI X 1 50 1 0 N A PCI X 0 66 0 0 N A PCI X 1 100 0 0 N A PCI X 0 133 Table 15 PCI B Clock Frequency Selection Straps P0_133_N P1_PCIX_N P1_M66EN MODE P0_AD 7 PCI_CLK_A MHz 1 1 0 PCI 1 25...

Page 75: ...ction Straps P0_133_N P0_PCIX_N P0_M66EN MODE P0_AD 21 23 22 P0_CLK PCI_CLK_A MHz CoreClock MHz 1 1 0 PCI 001 25 100 1 1 0 PCI 011 25 200 1 1 0 PCI 000 33 133 1 1 0 PCI 010 33 200 1 1 0 PCI 110 Reserved Reserved 1 1 1 PCI 001 50 100 1 1 1 PCI 011 50 200 1 1 1 PCI 000 66 133 1 1 1 PCI 010 66 200 1 1 1 PCI 110 Reserved Reserved 1 0 N A PCI X 001 50 100 1 0 N A PCI X 011 50 200 1 0 N A PCI X 000 66 1...

Page 76: ...load HyperTransport Link 0 and Link 1 frequency Table 17 P1_CLK Frequency Selection Straps P1_133_N P1_PCIX_N P1_M66EN MODE P0_AD 7 P1_CLK PCI_CLK_B MHz 1 1 0 PCI 1 25 1 1 0 PCI 0 33 1 1 1 PCI 1 50 1 1 1 PCI 0 66 1 0 N A PCI X 1 50 1 0 N A PCI X 0 66 0 0 N A PCI X 1 100 0 0 N A PCI X 0 133 This table is valid only when Tsi308 is operating in Tsi301 compatible mode The link frequencies are initiali...

Page 77: ...miconductor Corporation www tundra com 101 Reserved 110 Reserved 111 Reserved For proper functioning of Tsi308 Core clock should be greater than or equal to 1 4th HT Link Frequency DDR Table 18 Link Transmit Clock Frequency Selection Straps L0_clkSel P0_AD 29 27 L1_clkSel P0_AD 26 24 Lx_TX_CLK_H L MHz ...

Page 78: ...e clock that receives the data from Link 0 0 Async 1 Sync P0_AD 18 B10 Link 1 Sync Pointer Control When set indicates that Link 1 transmit clock is derived from the same time base as the receive clock in the device to which it is connected That means P0_CLK that is used by Tsi308 to generate L1_TX_CLK_H L should be used by the device that is connected to Tsi308 s Link 1 to generate its internal co...

Page 79: ...1 input buffers to be 5V tolerant 0 3 3 V 1 5 V P0_AD 31 B14 minRstCnt ALSC Reserved Must be set to 0 PLL_TESTENB AB1 Internal PLL Test Mode ALSC Reserved Should be set to 0 P0_BYPASS_E B3 PCI_A PLL Bypass Mmode ALSC Reserved Must be set to 0 P1_BYPASS_E AD3 PCI _B PLL Bypass Mode ALSC Reserved Must be set to 0 L0_TX_BYPASS_CLK AB2 HT Link 0 Transmit Bypass Clock ALSC Reserved Should be set to 0 L...

Page 80: ...led low during cold reset and deasserted after reset is complete SCAN_EN AB3 Scan Enable ALSC Reserved Should be set to 0 Used during scan shift hold operations of ATPG P0_OIR_DISCON_EVEN T A3 Reserved Must be set to 0 P1_OIR_DISCON_EVEN T AB23 Reserved Must be set to 0 SPARE_PIN_1 B2 REFCLK_C RefClk C REFCLK in Rev C mode STOP_P0 A2 ALSC Reserved Should be set to 0 Reserved for future use STOP_P1...

Page 81: ...or Corporation www tundra com 4 Register Descriptions This chapter discusses the following topics about Tsi308 s registers Configuration Registers on page 82 Summary of Configuration Registers on page 85 64 bit Address Remapping Capability Indices on page 89 ...

Page 82: ...X PCI devices 4 1 1 1 Single Tsi301 SP Mode In Single Tsi301 mode Tsi308 behaves just like previous generation Tsi301 chip from software s viewpoint It implements Tsi301 software compatible register set as specified in 5 so that existing software driver that is written for Tsi301 will work seamlessly In this mode device may not support some of the features that are defined in HT 1 05 specification...

Page 83: ...d non sharing dual hosted chain implementation and also allows the logical End Of Chain EOC to be set in any of the two links of either device Figure 6 Dual Tsi301 Mode 4 1 1 3 Tsi308 Single PCI X Mode GSP This mode implements standard HT 1 05 compliant tunnel device bridging to a single 64 bit PCI X bus that can be operated in traditional PCI mode as well The PCI X mode is compliant to 3 and the ...

Page 84: ...This mode supports both sharing and non sharing dual hosted chain implementation and also allows the logical End Of Chain EOC to be set in any of the two links of either device Figure 8 Tsi308 Dual PCI X Mode 4 1 2 Configuration Mechanism Configuration accesses are accepted from HyperTransport to the Tsi308 internal CSRs if they are Type 0 accesses with a device number equal to the value in the Ba...

Page 85: ...and return default values when read 4 2 3 Mode Encodings As described in previous sections the following abbreviations are used to denote various operating modes of Tsi308 SP Single Tsi301 mode Implements a 8 bit tunnel device Device A bridging to a single 64 bit PCI It uses CSR 0 only and Device B and corresponding CSR 1 is not visible to the software This mode supports both 32 and 64 bit PCI CSR...

Page 86: ...corresponding Device ID Indirectly accessed 64 bit Address Remapping Registers Indirectly accessed Interrupt Definition Registers Indirectly accessed SROM Registers Table 20 Tsi308 CSR Header Device ID Vendor ID 00 Status Command 04 Class Code Revision ID 08 BIST Header Type Primary Latency Timer Cache line 0C Base Address Register 0 10 Base Address Register 1 14 Sec Latency Timer Subordinate Bus ...

Page 87: ...ror Handling Enumeration Scratch Pad 54 Reserved Memory Limit Upper Memory Base Upper 58 Reserved Read Control 2 5C PCI Control 1 Read Control 1 60 Error Control 64 Reserved ParErr Report En HT Error Control 68 Reserved Transmit Control HT Rx Data Buffer Allocation 6C Link Impedance Control 0 70 Link Impedance Control 1 74 Capability Type Interrupt Discovery and Configuration Index Capability 3 Ca...

Page 88: ...r PCI Power Mgmt Capability ID C0 Data Bridge Support Extns Power Management Control Status Registers C4 Reserved Transmit Buffer Counter Max 0 C8 Reserved Transmit Buffer Counter Max 1 CC Reserved SMAF Field StoreForward Test port D0 Reserved Sri Index D4 Sri Data D8 Diagnostics Link 0 Receive CRC Expected DC Cap Type Address Mapping Extension Block Typ e I O Size of DMA Map Capability 5 Capabili...

Page 89: ...window defined in Table 21 will have Isoc bit set if bit 2 Isochronous of DMA Window Control Register DMACtrl0 is set Note that it will only affect the bit setting and Tsi308 still sends traffic through same three base virtual channels It doesn t implement dedicated Isochronous Virtual Channel buffers Table 21 64 bit Address Remap Indexed Registers Index 31 Index 0 00h SBNP Window Base Lower Reser...

Page 90: ...Semiconductor Corporation www tundra com 4 3 2 Read Control 2 Register The controls prefetch length prefetch count etc set in Read Control 2 register offset 5Eh 5Ch are used for upstream traffic that is passing through the address ranges of DMA window defined in Table 21 ...

Page 91: ...ero value when read in Rev C mode This is because these registers are used in IOAPIC mode also Table 22 Interrupt Definition Registers Bit R W Access Initial Value Field Name and Description 63 R C 0 Waiting for EOI If RQEOI is 1 then this bit is set by hardware when an interrupt request is sent and cleared by hardware when the EOI is returned Software may write a 1 to this bit to clear it without...

Page 92: ...ntrInfo 4 2 Message Type Some devices may allow only certain application specific combinations of message type with other bits 1 R W 0 Polarity For external interrupt sources when this bit is set the interrupt signal is active low When clear the interrupt signal is active high For internal interrupt sources this bit is reserved 0 R W 1 Mask When this bit is set interrupt messages will not be sent ...

Page 93: ...gister Offset 14h indirect through Sri Index located at offset D4h Bit R W Access Initial Value Field Name and Description 2 0 R 010b AvgWeight n The averaging weight The default value is 2 avg avg 1 2 n sample 2 n 7 3 R 00h Reserved Always reads 0 8 R 1b CalRunCntl default is Run 0 Æ Disable calibration 1 Æ Run when running CAL_OUT_RESULTS is continually updated 9 R 0b CMTermCntl Enable calibrati...

Page 94: ...d Description 2 0 R 010b AvgWeight n The averaging weight The default value is 2 avg avg 1 2 n sample 2 n 7 3 R 00h Reserved Always reads 0 8 R 1b CalRunCntl default is Run 0 Æ Disable calibration 1 Æ Run when running CAL_OUT_RESULTS is continually updated 9 R 0b CMTermCntl Enable calibration with common mode termination 0 Disable 1 Enable 10 R 1b EnRxTerm Enable Rx termination This value is passe...

Page 95: ...one Calibration Done This bit is set by hardware when the calibration sequence is done CalOutResults has a new value 9 R 0h CalAcqdTx Transmit Calibration Acquired diff avg sample 1 for Tx check Venkat 10 R 0h CalLostTx Transmit Calibration Lost CalAcqdTx 0 11 R 0h CalAcqdRx Receive Calibration Acquired diff avg sample 1 for Rx 12 R 0h CalLostRx Receive Calibration Lost CalAcqdRx 0 Bit R W Access ...

Page 96: ...one Calibration Done This bit is set by hardware when the calibration sequence is done CalOutResults has a new value 9 R 0h CalAcqdTx Transmit Calibration Acquired diff avg sample 1 for Tx check Venkat 10 R 0h CalLostTx Transmit Calibration Lost CalAcqdTx 0 11 R 0h CalAcqdRx Receive Calibration Acquired diff avg sample 1 for Rx 12 R 0h CalLostRx Receive Calibration Lost CalAcqdRx 0 Bit R W Access ...

Page 97: ... is described explicitly when there is a conflict 4 3 5 1 VendorID Register Register Offset 01h 00h 4 3 5 2 Device ID Register Register Offset 03h 02h Bit R W Access Initial Value Field Name and Description 15 0 R 14D9h Vendor ID This value is defined as 14D9h for Tundra Semiconductor Bit R W Access Initial Value Field Name and Description 15 0 R Derived from straps Device ID SP DSP This Device ID...

Page 98: ...reserved and reads 0 9 R 0 FastB2Ben This has no meaning for HyperTransport Always reads 0 8 R W 0 SerrEn SP DSP This enables system error interrupt pins FATAL_ERR_N and NONFATAL_ERR_N to be driven 0 SERR_N output driver disabled default 1 SERR_N output driver enabled GSP GDP If this bit is set Tsi308 floods all its outgoing links with sync packets when it detects an error that causes a sync flood...

Page 99: ...nt through warm reset 5 R 0 VGAPalSnpEn controls the bridge s response to VGA compatible palette write accesses If enabled the bridge decodes VGA palette accesses I O 3C6 3C8 and 3C9 as belonging on the secondary bus The Tsi308 does not support VGA palette snooping Always reads 0 4 R 0 MemWrInvEn controls the ability of the bridge to generate Memory Write and Invalidate transactions as a master on...

Page 100: ...0 MemSpaceEn Controls the bridge s response as a target to memory space accesses on the primary interface If clear the bridge will not accept any requests within the memory space range given below SP DSP 00_0000_0000 FC_FFFF_FFFF GSP GDP 0000_0000_0000_0000 0000_00FC_FFFF_FFFF 0 Disable memory space 1 Respond to memory space accesses Not persistent through warm reset 0 R W 0 IoSpaceEn controls the...

Page 101: ...y a bridge on its primary interface it may be cleared by writing a 1 to it Persistent through warm reset 0 No error signaled 1 Tsi308 has asserted FATAL_ERR_N or NONFATAL_ERR_N or initiated sync flooding on the HyperTransport chain 13 R C 0 Received Master Abort This bit reports the detection of a master abort termination by the bridge when it is the master of a transaction on its primary interfac...

Page 102: ...rror Detected This bit is used to report the detection of a parity error by the bridge when it is the master of the transaction HyperTransport doesn t have parity errors GSP GDP Master Data Error This bit is set by Tsi308 if Data Error Response bit of Command register is set and if Tsi308 issues a posted request on primary interface with Data Error bit set or accepts a response from primary interf...

Page 103: ...lways reads 0 GSP GDP Interrupt Status This bit reflects the state of legacy INTx logic in the device regardless of the state of the Interrupt Disable bit in the Command register A 1 indicates that the interrupt source is active A 0 indicates that the interrupt is inactive Tsi308 doesn t support it Treated as reserved and reads 0 2 0 R 0h Reserved always reads 0 Bit R W Access Initial Value Field ...

Page 104: ...W Access Initial Value Field Name and Description 7 0 R W 00h Cache Line Size in bytes Must be a power of 2 This value is used to control generation of MemRdLine MemRdMult and MemWrInv commands by the PCI master when forwarding memory accesses from HT If this value is left 0 the Tsi301 only generates MemRd and MemWr commands For non zero values reads greater than 1 DW to prefetchable space generat...

Page 105: ...itial Value Field Name and Description 7 0 R 00h Primary Latency Timer This is not used by the Tsi308 Always reads 0 Bit R W Access Initial Value Field Name and Description 7 0 R 01h or 81h based on strap value Type A value of 01h indicates that this is a bridge header A value of 81h indicates this is a multi functional header in RevC mode Bit R W Access Initial Value Field Name and Description 7 ...

Page 106: ...19h Bit R W Access Initial Value Field Name and Description 31 0 R 00000000h Not used in the Tsi308 Always reads 0 Bit R W Access Initial Value Field Name and Description 7 0 R W 00h Primary Bus Number PCI bus number of the HyperTransport chain on which the Tsi308 is located Not persistent through warm reset Bit R W Access Initial Value Field Name and Description 7 0 R W 00h Secondary Bus Number P...

Page 107: ...stent through warm reset Bit R W Access Initial Value Field Name and Description 7 3 R W 00010 Timer Controls how long the Tsi308 may continue to occupy the PCI X Bus once the arbiter has taken the grant away in PCI clocks Not persistent through warm reset 2 0 R 000 Lower bits of Timer Hardwired to zero to indicate eight clock granularity Bit R W Access Initial Value Field Name and Description 7 4...

Page 108: ...t Address Register Register Offset 1Dh Bit R W Access Initial Value Field Name and Description 7 4 R W 0h Address Bits 15 12 of the top of the I O range 11 0 are assumed to be 1 leading to a 4KB granularity Not persistent through warm reset 3 0 R 1h Capability Indicates the size of I O addresses supported by the device is 32 bits ...

Page 109: ...the detection of a system error by a bridge on its secondary interface It may be cleared by writing a 1 to it Persistent through warm reset 0 No error detected 1 P_SERR_N assertion detected on the Tsi308 PCI bus 13 R C 0 Received Master Abort This bit reports the detection of a master abort termination by the bridge when it is the master of a transaction on its secondary inter face It may be clear...

Page 110: ...ons are all true Tsi308 is the bus master of the transaction on the secondary interface Tsi308 asserted PERR read transaction or detected PERR asserted write transaction The Parity Error Responses bit in the Bridge Control Register is set It is cleared by writing a 1 to the bit Not persistent through warm reset 0 No parity error detected 1 Parity error detected 7 R 1b Fast Back2Back Capability The...

Page 111: ...arm reset 3 0 R 0h These bits are read only and return zeros when read Only 32 bit addressing is supported Bit R W Access Initial Value Field Name and Description 15 4 R W 000h Address Bits 31 20 of the top inclusive of the memory range Not persistent through warm reset 3 0 R 0h These bits are read only and return zeros when read Only 32 bit addressing is supported Bit R W Access Initial Value Fie...

Page 112: ...nclusive of the prefetchable memory range Not persistent through warm reset 3 0 R 1h Indicates whether the bridge supports 32 or 64 bit addressing for prefetch able memory space 0 32 bit addressing 1 64 bit addressing Bit R W Access Initial Value Field Name and Description 31 8 R SP DSP R W GSP GDP 0h As Tsi301 does not support Addresses above 1012GB these bits are reserved and reads zero These bi...

Page 113: ...not support Addresses above 1012GB these bits are reserved and reads zero These bits are used in Tsi308 mode as address extension 63 40 is supported 7 0 R W 0h Address Bits 39 32 of the prefetchable memory range limit Not persistent through warm reset Bit R W Access Initial Value Field Name and Description 15 9 R W 00h Address SP DSP Reserved Tsi301 mode doesn t support decode of address bits abov...

Page 114: ... 38h Bit R W Access Initial Value Field Name and Description 15 9 R W 00h Address SP DSP Reserved Tsi301 mode doesn t support decode of address bits above 24 GSP GDP Bits 31 25 of the I O range limit Not persistent through warm reset 8 0 R W 000h Address Bits 24 16 of the I O range limit Not persistent through warm reset Bit R W Access Initial Value Field Name and Description 7 0 R 40h Pointer Reg...

Page 115: ...er Offset 3Ch 4 3 5 32 Interrupt Pin Register Register Offset 3Dh Bit R W Access Initial Value Field Name and Description 7 0 R W FFh Register The HyperTransport spec requires that this be a read write register Its value is not used internally Not persistent through warm reset Bit R W Access Initial Value Field Name and Description 7 0 R 00h Reserved ...

Page 116: ...s both the HT links with sync packets Not persistent through warm reset 10 R C 0 DiscardStat this bit is set by hardware when a request is dropped due to an expired discard counter It may be cleared by writing a 1 to it Persistent through warm reset 9 R W 0 SecDiscardTimer Sets the length of the timer on delayed requests Once the initial subrequests of an inbound delayed transaction have completed...

Page 117: ... will be treated as an error returning error returning a Target Abort Response indicated on HyperTransport by a set error bit without NXA for nonposted requests For posted requests Tsi308 floods both the HT links with sync packets if SERR Enable bit in the Command register is set Not persistent through warm reset 4 R 0 Reserved 3 R W 0 VgaEn This bit modifies the response by the bridge to VGA comp...

Page 118: ...ters that are in the first 64 Kbytes of PCI I O address space After reset the default state of this bit must be 0 Not persistent through warm reset If this bit is set when the address mapping extensions are in use the address decode behavior or the device may be undefined 1 R W 0 SerrEn SP DSP This bit controls forwarding of system errors from the secondary interface to the primary interface If it...

Page 119: ...ith sync packets if SERR Enable bit in the Command register is set Sets Parity Error Detected bit in its secondary status register Sets SERR Signaled bit of the status register If Tsi308 has claimed the cycle and terminated it by signaling a Target Abort then Signaled Target Abort bit in its secondary status register is also set Data Parity Error If Tsi308 detects data parity error when it is the ...

Page 120: ...primary block it is always 000b 12 R SP DSP R W GSP GDP 0 SP DSP Reserved GSP GDP Drop on Uninitialized Link This bit controls the packet forwarding behavior of Tsi308 when both End of Chain and Initialization Complete bits of Link Control register of receiving link are clear When Drop on Uninitialized Link bit is set Tsi308 behaves as if End of Chain bit is set if it receives packets when Initial...

Page 121: ...m whenever the HyperTransport Command register is written In DSP and GDP mode this bit is 1 b0 in the CSR of nearer link and is 1 b1 in the CSR of farther link This bit is updated with the link number in SP and GSP mode 9 5 R 01h Unit Count The number of UnitIDs consumed This number is always 1 4 0 R W 00h Base Unit ID This is the base of the range of HyperTransport UnitIDs occupied by this device...

Page 122: ...is set then for requests from PCI PCI X that access above FF FFFF FFFFh Tsi308 uses Address Extension command to forward them onto HT Not persistent through warm reset 14 R C SP DS P R W GSP GDP 0 SP DSP NXA Error This bit is set whenever a response or posted write is dropped due to hitting end of chain It can be cleared by writing a 1 to it Persistent through warm reset GSP GDP Extended CTL Time ...

Page 123: ... that this link is not part of the logical Hyper Transport chain and that this device should be considered the end of the chain for packets coming from the other direction Packets directed toward this link are dropped Nonposted requests result in nonexistent address NXA error responses It may only be set not cleared by software Not persistent through warm reset 5 R 0 Init Done This read only bit i...

Page 124: ...he test sequence has completed hardware will clear the bit Not persistent through warm reset 1 R W 0 CRC Sync Flood Enable if set this bit causes CRC errors to be treated as fatal errors When detected they will cause all HyperTransport links from this device to be flooded with sync packets and the LinkFail bit to be set Not persistent through warm reset 0 R 0 Reserved Bit R W Access Initial Value ...

Page 125: ...sed width of the outgoing link from this device It must match the used incoming width of the device on the other end of the link 100b 2 bits 101b 4 bits 000b 8 bits 001b 16 bits 011b 32 bits SP DSP Only supports 8 bits GSP GDP Supports 2 4 or 8 bits Tsi308 hardware initializes this register based on the result of link width negotiation sequence Software can write a different value to this register...

Page 126: ...32 bits SP DSP Supports only 8 bit wide link GSP GDP Supports 2 4 or 8 bits Initialized by Tsi308 hardware after cold reset based on the results of the link width negotiation sequence Software can then write a different value into this register The chain must pass through warm reset sequence for the new width values to be reflected on the link 7 R 0 SP DSP Reserved GSP GDP Doubleword Flow Control ...

Page 127: ...th of 8 bits 100b 2 bits 101b 4 bits 000b 8 bits 001b 16 bits 011b 32 bits 3 R 0 SP DSP Reserved GSP GDP Doubleword Flow Control In DwFcIn Tsi308 doesn t support it and always reads 0 2 0 R 000b Max Link Width In Indicates the maximum width of the incoming link supported by this device Supports the maximum width of 8 bits 100b 2 bits 101b 4 bits 000b 8 bits 001b 16 bits 011b 32 bits Bit R W Access...

Page 128: ... tundra com 4 3 5 39 HyperTransport Link 1 Control Register Tsi308 uses HyperTransport Link 0 Control of CSR0 for Link0 and HyperTransport Link 0 Control of CSR1 for Link1in GDP and DSP modes HyperTransport Link 1 Control of CSR0 is used for Link1 in SP and GSP modes CSR1 is not visible in these modes ...

Page 129: ...at access above FF FFFF FFFFh Tsi308 uses Address Extension command to forward them onto HT Not persistent through warm reset 14 R C SP R DSP R W GSP GDP 0 SP NXA Error This bit is set whenever a response or posted write is dropped due to hitting end of chain It can be cleared by writing a 1 to it Persistent through warm reset DSP Not used Reads 0 GSP GDP Extended CTL Time If this bit is set durin...

Page 130: ... EOC bit should always be set prior to setting the XmitOff bit It may only be set by software not cleared It may only be cleared by a warm or cold reset sequence on HyperTransport DSP GDP Not used Reads 0 6 R S SP R GSP R DSP GDP 0 SP GSP End Of Chain this bit indicates that this link is not part of the logical Hyper Transport chain and that this device should be considered the end of the chain fo...

Page 131: ... 1 bad CRC will be generated on all outgoing traffic on the link Not persistent through warm reset DSP GDP Not used 2 R S SP R GSP R DSP GDP 0 SP GSP CRC Start Test Writing a 1 to this bit causes hardware to initiate a CRC test sequence on the link When the test sequence has completed hardware will clear the bit Not persistent through warm reset DSP GDP Not used 1 R W 0 SP GSP CRC Sync Flood Enabl...

Page 132: ...iguration Register Tsi308 Tsi308 uses Link0 Width Control SP Link0 Configuration Register Tsi308 of CSR0 for Link0 and Link0 Width Control SP Link0 Configuration Register Tsi308 of CSR1 for Link1in GDP and DSP modes Link 1 Width Control SP Link 1 Configuration Register Tsi308 of CSR0 is used for Link1 in SP and GSP modes CSR1 is not visible in these modes ...

Page 133: ...s device It must match the used incoming width of the device on the other end of the link 100b 2 bits 101b 4 bits 000b 8 bits 001b 16 bits 011b 32 bits SP Only supports 8 bits GSP Supports 2 4 or 8 bits Tsi308 hardware initializes this register based on the result of link width negotiation sequence Software can write a different value to this register but chain must pass through warm reset sequenc...

Page 134: ...its SP Supports only 8 bit wide link GSP Supports 2 4 or 8 bits Initialized by Tsi308 hardware after cold reset based on the results of the link width negotiation sequence Software can then write a different value into this register The chain must pass through warm reset sequence for the new width values to be reflected on the link GDP DSP Not used 7 R 0 SP DSP GDP Reserved GSP Doubleword Flow Con...

Page 135: ...th of 8 bits 100b 2 bits 101b 4 bits 000b 8 bits 001b 16 bits 011b 32 bits 3 R 0 SP DSP Reserved GSP GDP Doubleword Flow Control In DwFcIn Tsi308 doesn t support it and always reads 0 2 0 R 000b Max Link Width In Indicates the maximum width of the incoming link supported by this device Supports the maximum width of 8 bits 100b 2 bits 101b 4 bits 000b 8 bits 001b 16 bits 011b 32 bits Bit R W Access...

Page 136: ...e and Description 7 5 R 0h SP DSP 1h GSP G DP MajorRevision This field contains the major revision of the HT I O Link Protocol Specification to which this chip confirms to SP DSP Reads 3 b000 GSP GDP Reads 3 b001 4 0 R 10001b SP DSP 5 b00101 GSP GDP MinorRevision This field contains the minor revision of HT I O Link Protocol Specification to which this chip confirms to SP DSP Reads 5 b10001 GSP GD...

Page 137: ... GDP End Of Chain Error This bit is set when a link transmitter receives a posted or response packet to be sent out when the link is the end of chain This applies to forward packets received by this link as well as packets received by this link s transmitter from PCI PCI X interfaces A link s transmitter is said to be End Of Chain if either End of Chain bit is set in link control register or Initi...

Page 138: ...nfatal error interrupts Persistent through warm reset 3 0 R SP DSP R W GSP GDP 0 SP DSP Reserved GSP GDP Link Frequency Specifies the operating frequency of the link s transmitter clock The data rate is twice this value The encoding of this field is shown below 0000 200 MHz default 0001 300 MHz 0010 400 MHz 0011 500 MHz 0100 600 MHz If the register comes up 0000 at cold reset software can write it...

Page 139: ... clock frequency capabilities of the link Each bit in LinkFreqCap corresponds to one of the 16 possible encodings of Link Frequency register Bit N of LinkFreqCap corresponds to encoding N of the LinkFreq field A 1 in LinkFreqCap means that the link supports the corresponding link frequency and a 0 means the link doesn t support that frequency Following table shows the maximum HT link frequency tha...

Page 140: ...Disable When set Tsi308 orders traffic in all UnitIDs together within each virtual channel to support passive UnitID Clumping Tsi308 always orders traffic in all UnitIDs together regardless of this bit setting by software 4 R 1b 64 Bit Addressing If set indicates that Tsi308 supports 64 bit addresses by accepting and forwarding Address Extension command doublewords 3 R 0b Extended CTL Time Require...

Page 141: ...ransmitter receives a posted or response packet to be sent out when the link is the end of chain This applies to forward packets received by this link as well as packets received by this link s transmitter from PCI PCI X interfaces A link s transmitter is said to be End Of Chain if either End of Chain bit is set in link control register or Initialization Complete bit is clear and Drop On Uninitial...

Page 142: ...rrupts Persistent through warm reset GDP Not used 3 0 R W GSP GDP 0 GSP Link Frequency Specifies the operating frequency of the link s transmitter clock The data rate is twice this value The encoding of this field is shown below 0000 200 MHz default 0001 300 MHz 0010 400 MHz 0011 500 MHz 0100 600 MHz If the register comes up 0000 at cold reset software can write it to either 0000 through 0100 and ...

Page 143: ...on core clock frequency GSP Link Frequency Capability Register LinkFreqCap It is a 16 bit read only register that indicates the clock frequency capabilities of the link Each bit in LinkFreqCap corresponds to one of the 16 possible encodings of Link Frequency register Bit N of LinkFreqCap corresponds to encoding N of the LinkFreq field A 1 in LinkFreqCap means that the link supports the correspondi...

Page 144: ...tal error interrupt NONFATAL_ERR_N to be asserted whenever any of the CRC Error bits are asserted in either of the Link Control registers Not persistent through warm reset 13 R W 0h Response Error NonFatal Enable When asserted this bit will cause the fatal error interrupt NONFATAL_ERR_N to be asserted whenever the Response Error bit 9 of this register bit is asserted Not persistent through warm re...

Page 145: ... W 0h CRC Error Fatal Enable When asserted this bit will cause the fatal error interrupt FATAL_ERR_N to be asserted whenever any of the CRC Error bits are asserted in either of the Link Control registers Not persistent through warm reset 5 R W 0h Response Error Fatal Enable When asserted this bit will cause the fatal error interrupt FATAL_ERR_N to be asserted whenever the Response Error bit 9 of t...

Page 146: ...use the link to be flooded with Sync packets whenever the Overflow Error bit is asserted in one of the Link Error registers Not persistent through warm reset 0 R W 0h Protocol Error Flood Enable When asserted this bit will cause the link to be flooded with Sync packets whenever the Protocol Error bit is asserted in one of the Link Error registers Not persistent through warm reset Bit R W Access In...

Page 147: ... MemRdMult before allowing the PCI requester to reconnect Not persistent through warm reset 15 12 R W 0h Reserved 11 R W 0 Line Prefetch Continue If set and prefetching for MemRdLine commands is enabled MemRdLine and MemRd if prefetching is enabled for MemRd commands prefetching will be continuous As each line of data is returned to PCI another line will be read from HyperTransport creating a movi...

Page 148: ...reset 4 2 R W 000b Multiple Prefetch Count This indicates the number of lines to be prefetched for MemRdMult commands in addition to the line containing the original request address MemRdMults always prefetch at least to the end of the first line Not persistent through warm reset 1 R W 0 Mem Rd Prefetch Enable if set PCI MemRd commands are treated as prefetchable using the same prefetch controls a...

Page 149: ...e will be read from HyperTransport creating a moving prefetch window Otherwise prefetching will end when the specified number of lines has been fetched Not persistent through warm reset 10 R W 0 MultPrefetchContinue If set and prefetching for MemRdMult commands is enabled MemRdMult prefetching will be continuous As each line of data is returned to PCI another line is read from HyperTransport creat...

Page 150: ...ne Not persistent through warm reset 1 R W 0 Mem Rd Prefetch Enable if set PCI MemRd commands are treated as prefetchable using the same prefetch controls as for memRdLine other Wise no prefetching is performed for MemRds and they fetch only the initially requested DW or QW Not persistent through warm reset 0 R W 0b SP DSP 1b GSP G DP Prefetch Enable This bit enables prefetching for prefetchable r...

Page 151: ...d and the first beat of data Not persistent through warm reset Tsi308 hardware doesn t use this value It is ignored even when in Tsi301 mode 4 R W 0h Park Master This bit controls where the arbiter defaults to when there is no PCI PCI X request outstanding The default can be to grant the PCI PCI X bus to P_GNT0_N assumed to be connected to Tsi308 or to grant the PCI bus to the most recent master o...

Page 152: ...Parity Error Response Enable 1 Not persistent through warm reset 28 R W 0 Discard SERR Fatal If a secondary bus discard timer expiration occurs with the Discard Timer SERR Enable DiscardSerrEn asserted this bit controls whether the SERR gets mapped to a fatal or nonfatal interrupt 0 Nonfatal 1 Fatal Not persistent through warm reset 27 R C 0 Response Match Error This chip received a response packe...

Page 153: ...rEn in the Command Not persistent through warm reset 18 R W 0 Post Fatal Enable If asserted PCI master posted writes that fail to complete successfully on the bus result in a fatal interrupt assertion if enabled by SerrEn in the Command register Not persistent through warm reset 17 R C 0 Retry Timeout A master transaction was retried beyond the value in Retry Timer Not persistent through warm rese...

Page 154: ...warm reset 10 R W 0h CrcNonFatalEn CRC Nonfatal Enable If asserted detecting a HyperTransport CRC error causes a nonfatal interrupt Not persistent through warm reset 0 Disable 1 Enable 9 R W 0h CrcFatalEn If asserted detection of a HyperTransport CRC error causes a fatal interrupt Not persistent through warm reset 0 Disable 1 Enable 8 R W 0h NxaSyncFloodEn If asserted detection of a posted HT requ...

Page 155: ...eive buffer overflow error causes a nonfatal interrupt Not persistent through warm reset 0 Disable 1 Enable 3 R W 0h OvfFatalEn If asserted detection of a HyperTransport receive buffer overflow error causes a fatal interrupt Not persistent through warm reset 0 Disable 1 Enable 2 R W 0h ProtSyncFloodEn If asserted detection of a protocol error causes sync flooding and the LinkFail bit to be set Not...

Page 156: ... PCI2HT packets will wait for two pci clock cycles to monitor the PERR on the bus if any This will add up the latency by two pci clock cycles This parity checking will be reported as Data Error on HT Bit R W Access Initial Value Field Name and Description 15 14 R 00b Reserved 13 12 R W 01b WantPReq The number of buffers minus one to try to keep released in the posted request channel Not persistent...

Page 157: ...uffer allocation to the nonposted request channel Not persistent through warm reset 0 1 R W 01b NeedResp The minimum data buffer allocation to the response channel Not persistent through warm reset Bit R W Access Initial Value Field Name and Description 3 0 R W 4h BufRelSpace controls the throttling of buffer release messages on a busy bus If the bus is idle buffer releases always get issued immed...

Page 158: ...mit pull down resistor 21 17 R 00h Current RxTerm current impedance value for receive termination resistor 16 12 R W 10h RxTerm impedance value for receive termination resistor Used when RxSel is set Not persistent through warm reset 11 R W 0 RxSel enables use of CSR receive impedance values Not persistent through warm reset 10 6 R W 10h TxUp impedance value for transmit pull up resistor Used when...

Page 159: ...lue for receive termination resistor 16 12 R W 10h Rx Term Impedance value for receive termination resistor Used when RxSel is set Not persistent through warm reset 11 R W 0 Rx Select Enables use of CSR receive impedance values Not persistent through warm reset 10 6 R W 10h Tx Up Impedance value for transmit pull up resistor Used when TxSel is set Not persistent through warm reset 5 1 R W 00h Tx D...

Page 160: ...hey are valid in GSP GDP modes Register Offset 7Fh 7Ch 4 3 5 65 Reserved Registers Register Offset 9Fh 80h Bit R W Access Initial Value Field Name and Description 31 24 R 80h Indicates that this is an interrupt discovery and configuration block 23 16 R W 00h Index Points to the indexed location 15 8 R B4h Points to next capability register 7 0 R 08h HT Capability ID Bit R W Access Initial Value Fi...

Page 161: ...ription 15 R W 0b Interrupt Enable 0 Disabled 1 Enabled 14 R W 0b Destination Mode 0 Physical 1 Logical 13 6 R W FFh Destination ID 5 4 R W 00b Message Type Not persistent through warm reset 00 Fixed 01 Arbitrated 10 SMI 11 NMI 3 R W 0b Polarity Active polarity of interrupt 0 Active low 1 Active High 2 R W 0b Trigger Mode Level Edge trigger Not persistent through warm reset 0 Edge 1 Level 1 0 R W ...

Page 162: ...d 1 Enabled 14 R W 0b Destination Mode 0 Physical 1 Logical 13 6 R W FFh Destination ID 5 4 R W 00b Message Type Not persistent through warm reset 00 Fixed 01 Arbitrated 10 SMI 11 NMI 3 R W 0b Polarity Active polarity of interrupt 0 Active low 1 Active High 2 R W 0b Trigger Mode Level Edge trigger Not persistent through warm reset 0 Edge 1 Level 1 0 R W 00b Vector Interrupt vector Not persistent t...

Page 163: ...le Register These registers are valid only in GSP GDP modes Register Offset BFh BDh Bit R W Access Initial Value Field Name and Description 31 27 R 10010b Unit ID Clumping Capability 26 16 R 00h Reserved 15 8 R E0h Capability 4 Next Capability pointer 7 0 R 08h HT Capability ID Bit R W Access Initial Value Field Name and Description 31 1 R 0h Reads Zero as Tsi308 does not clump 0 R 0h Reserved Bit...

Page 164: ...ability Pointer Register Register Offset C1h Bit R W Access Initial Value Field Name and Description 7 0 R 01h GSP GDP 0h S P DSP SP DSP Reserved GSP GDP Capability ID This field when 01h identifies the linked list item as being the PCI Power Management registers Bit R W Access Initial Value Field Name and Description 7 0 R 00h GSP GDP 00h SP DSP SP DSP Reserved GSP GDP Next Cap Pointer Points to ...

Page 165: ...rom the pin This bit is cleared by hardware once the interrupt is sent This bit cannot be written by S W once it s set It can be written by S W only after hardware clears this bit Not persistent through warm reset 5 R 0 Active If 1 the given pin has an asserted level interrupt Not persistent through warm reset 4 0 R W 00000b Pin Number Determines which pin the Activate and Initiate fields affect 0...

Page 166: ...do not support D2 state and returns zero 9 R 0 D1_Support 0 this function do not support D1 state and returns zero 8 6 R 0b Aux_Current Indicates that there is no requirement for auxiliary current as D3Cold device power state is not supported 5 R 0b DSI Indicates that there is no special initialization requirement 4 R 0b Reserved 3 R 0b PMECLK Indicates that the PCI clock is required for PME gener...

Page 167: ...able 5 0 R W 000000b Block Vector Upper vector bits for Block2 Interrupts Not persistent through warm reset Bit R W Access Initial Value Field Name and Description 15 R 0b Note PME_STS PME Status This bit reads zero as Tsi308 does not support PME 14 9 R 000000b Note Reserved 8 R 0b Note PME_EN PME Enable As per spec it s a R W Since Tsi308 does not support PME this bit is hardwired to zero 7 2 R 0...

Page 168: ...eserved These are reserved in all modes Register Offset C7h Bit R W Access Initial Value Field Name and Description 7 1 R 0h Reserved in all modes 0 R 0b SP DSP Reserved GSP GDP BPCC_EN 0 bus power clock control policies defined in PCI Bus Power Management Interface Specification Section 4 7 1 have been disabled Bit R W Access Initial Value Field Name and Description 7 0 R 0h Reserved ...

Page 169: ...RCmd response command buffer threshold Not persistent through warm reset 15 12 R W Fh NpData nonposted data buffer threshold Not persistent through warm reset 11 8 R W Fh NpCmd nonposted command buffer threshold Not persistent through warm reset 7 4 R W Fh Pdata posted data buffer threshold Not persistent through warm reset 3 0 R W Fh PCmd posted command buffer threshold Not persistent through war...

Page 170: ... com 11 8 R W Fh NpCmd nonposted command buffer threshold Not persistent through warm reset 7 4 R W Fh Pdata posted data buffer threshold Not persistent through warm reset 3 0 R W Fh PCmd posted command buffer threshold Not persistent through warm reset Bit R W Access Initial Value Field Name and Description ...

Page 171: ...r Offset D0h Bit R W Access Initial Value Field Name and Description 7 R W 0h Tst_DO data from the bus input 6 R W 0h Tst_DI data to the bus output 5 R W 0h Tst_MS signal output 4 R W 0h Tst_Mod1 signal output 3 R W 0h Tst_Mod0 signal output 2 R W 0h Tst_Clk signal output 1 R W 0h DIO Direction It selects the direction of Tst_DIO 0 output 1 input 0 R W 0h Tst_DIO signal Input Output Its direction ...

Page 172: ...erns are driven using these bits after warm reset or secondary bus reset in PCIX mode These registers can be programmed regardless of the status of secondary bus reset Programmed values will take effect only when the secondary bus is in reset via s w 00 25 MHz to 50 MHz 01 50 MHz to 66 MHz 10 66 MHz to 100 MHz 11 100 MHz to 133 MHz 1 R W 1h Store and Issue mechanism for posted non posted and respo...

Page 173: ...cted Register These registers are valid only in SP DSP modes They are reserved in other modes Register Offset DFh DCh Bit R W Access Initial Value Field Name and Description 31 8 R 0h Reserved 7 0 R W 0h Sri Index Points to the location where values from SriData has to be written or read Bit R W Access Initial Value Field Name and Description 31 0 R 0h Sri Data Data is read in the location pointed...

Page 174: ...DP modes Register Offset E0h 4 3 5 91 Capability 5 Register These registers are valid only in GSP GDP modes Register Offset E1h Bit R W Access Initial Value Field Name and Description 7 0 R 08h Id HT Capability ID assigned by the PCI SIG Bit R W Access Initial Value Field Name and Description 7 0 R F0h Pointer pointer to the next capability block It points to PCI X capability registers ...

Page 175: ...dress remapping Always reads 10100b indicating this is a HyperTransport 64 bit address remapping 10 9 R 1h MapType This field is 1h to indicate that Tsi308 implements 64 bit address remapping 8 4 R W 00h IOSize This field defines the number of bits of downstream IO addresses are discarded The default is 0 to pass all 25 bits of a HyperTransport technology IO cycle All discarded bits are 0s on the ...

Page 176: ...ional The following tables show the value they hold in GSP GDP modes Register Offset F0h Bit R W Access Initial Value Field Name and Description 31 0 R W 0000_0000 h DataLower This is the lower 32 bit of the 64 bit address remap indexed registers accessed through the Idx field above Bit R W Access Initial Value Field Name and Description 31 0 R W 0000_0000 h DataUpper This is the upper 32 bit of t...

Page 177: ...e to what mode and in PCI X mode what frequency the bridge set the secondary bus the last time secondary RST was asserted 0 conventional mode 1 66 MHz 2 100 MHz 3 133 MHz 4 5 6 7 are reserved 5 R C 0 Split Request Delayed write 1 to clear This bit is set any time the bridge has a request to forward a transaction on the secondary bus but cannot because there is not enough room within the limit spec...

Page 178: ...ards a split completion Once set this bit remains set until software writes a 1 to this location 1 R 1 133 MHz capable This bit indicates bridge s secondary bus interface is capable of 133 MHz 0 R 1 CSR0 0 CSR1 64 bit Device This bit indicates the width of the bridge s secondary AD s interface 0 32 bit device 1 64 bit device Device 0 can act as 64 bit in SP GSP modes Device 1 is not visible in the...

Page 179: ...ave these registers to its default values 15 0 R 5h Split Transaction Capacity Indicates the size of the buffer used for storing Split completion for requesters on the secondary bus addressing completers on the primary bus Bit R W Access Initial Value Field Name and Description 31 16 R W 6h Split Transaction Commitment Limit Indicates the cumulative size for all memory read transactions forwarded ...

Page 180: ...cratch Register These registers are multifunctional and they hold the following values in SP DSP modes Register Offset FFh FCh Bit R W Access Initial Value Field Name and Description 31 0 R Expected CRC value for Link 1 This register is for software use and will survive cold and warm reset as long as there is no power off Bit R W Access Initial Value Field Name and Description 31 0 R Received CRC ...

Page 181: ... are available in the Function1 pci configuration space for PCI A PCI B These registers are valid only in GSP GDP and RevC mode They are not visible in other modes as Tsi308 will be a single function device in those modes In GSP GDP and RevC mode Interrupts can be programmed only by IOAPIC register set whereas in other modes it can be programmed by Interrupt Discovery registers Device ID Vendor ID...

Page 182: ... Bit R W Access Initial Value Field Name and Description 31 16 R 9001h IOAPIC Device ID 15 0 R 1142h Vendor ID Bit R W Access Initial Value Field Name and Description 31 3 R 0200_000 0h Default state 2 R W 0h PCI Master Enable 1 Enables IOAPIC to initiate the interrupts to host 1 R W 0h Memory Enable 1 Enables acess to the memory space specified at 10h 0 R 0h Default state Bit R W Access Initial V...

Page 183: ... INDEX Register 03 00h 4 3 7 2 IOAPIC DATA Register 13 10h Bit R W Access Initial Value Field Name and Description 63 12 R W 0000_00 00_0000 _0h IOAPIC BAR Specifies the IOAPIC register set address space 11 0 R 004h Hardwired to indicate a 4KB block of 64 bit non prefetchable memory space Bit R W Access Initial Value Field Name and Description 31 8 R 0h Reserved 7 0 R W 0h Index It selects the IOA...

Page 184: ...ng the APIC bus should have a unique APIC ID 00h 23 0 R 0h Reserved Address Offset Bit R W Access Initial Value Field Name and Description 01h 31 24 R 0h Reserved 01h 23 16 R 09h Maximum Redirection Entry This field contains the entry number 0 being the lowest entry of the highest entry in the I O Redirection Table The value is equal to the number of interrupt input pins for the IOAPIC minus one T...

Page 185: ...itration priority for the IOAPIC 02h 23 0 R 0h Reserved Address Offset Bit R W Access Initial Value Field Name and Description 10h 31 0 R W 0h INTR0 31 0 11h 31 0 R W 0h INTR0 63 32 12h 31 0 R W 0h INTR1 31 0 13h 31 0 R W 0h INTR1 63 32 14h 31 0 R W 0h INTR2 31 0 15h 31 0 R W 0h INTR2 63 32 16h 31 0 R W 0h INTR3 31 0 17h 31 0 R W 0h INTR3 63 32 18h 31 0 R W 0h INTR4 31 0 19h 31 0 R W 0h INTR4 63 3...

Page 186: ...s set the interrupt is masked 15 R W 0h Intr Info 5 Request EOI If set after each interrupt request is sent the device waits for the Waiting for EOI bit to be cleared before sending another interrupt 14 R O 0h Waiting for EOI If RQEOI is 1 then this bit is set by hardware when an interrupt request is sent and cleared by hardware when the EOI is returned 13 R W 0h Polarity For external interrupt so...

Page 187: ...4 Register Descriptions 187 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 188: ...4 Register Descriptions 188 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 189: ...ut Timing Characteristics on page 194 HyperTransport Input Timing Characteristics on page 196 HyperTransport Interconnect Timing Characteristics on page 198 HyperTransport Transfer Timing Characteristics on page 199 HyperTransport Impedance Requirements on page 201 HyperTransport DC Electrical Characteristics on page 203 Reset Timing on page 204 Power Consumption on page 206 Thermal Data on page 2...

Page 190: ...itter Amount of time the reference clock or signal edge can vary on either the rising or falling edges TDO Data out Amount of time after the reference clock edge that the output will become valid The minimum time represents the data output hold The maximum time represents the earliest time the designer can use the data TZD Z state to data valid Amount of time after the reference clock edge that th...

Page 191: ...Amount of time the input or output is active Table 24 Typical AC Timing Values Symbol Conditions Bidirectional Output Units Min Nom Max Min Nom Max Frequency DC 100 DC 100 MHz TCLK 10 DC 10 DC ns TCLKH 30 70 30 70 TCLKL 30 70 30 70 TRISE 2 2 pF 0 37 0 27 ns 27 pF 2 36 1 83 ns 53 pF 4 74 3 54 ns 78 pF 7 31 5 33 ns 100 pF 9 92 7 13 ns TFALL 2 2 pF 0 30 0 25 ns 27 pF 2 30 1 80 ns 53 pF 4 82 3 58 ns 7...

Page 192: ...s 192 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com TSU 4 4 ns THLD 1 1 ns TPW 10 10 ns Table 24 Typical AC Timing Values Symbol Conditions Bidirectional Output Units Min Nom Max Min Nom Max ...

Page 193: ... 66 MHz 100 MHz 133 33 MHz Units Min Max Min Max Min Max Min Max Min Max Min Max Frequency 24 95 25 05 33 27 33 40 49 9 50 1 66 53 66 8 99 8 100 2 133 07 133 6 MHz TCLK 39 92 40 08 29 94 30 06 19 96 20 04 14 97 15 03 9 98 10 02 7 49 7 51 ns TCLKH 12 28 9 21 6 14 4 5 10 5 3 7 2 25 5 25 ns TCLKL 12 28 9 21 6 14 4 5 10 5 3 7 2 25 5 25 ns TRISE 0 05 0 5 0 05 0 5 0 05 0 5 0 05 0 5 0 05 0 5 0 05 0 5 ns ...

Page 194: ...the time difference measured in a single ended fashion at the midpoint of the transition of the true signal and the midpoint of the transition of the complement signal Differential output skew is limited primarily by DVOCM such that at the given minimum output edge rate differential skew would cause a violation of DVOCM before violating the output differential skew specification Figure 11 TODIFF T...

Page 195: ...ge at the receiver and therefore allows for simple data recovery TCADV_MIN is measured at the device pins from the crossing point of either the latest TX_CAD CTL transition to the crossing point of the TX_CLK transition or the TX_CLK transition to the earliest TX_CAD CTL transition TCADV_MAX is measured at the device pins from either the crossing point of the earliest TX_CAD CTL transition to the ...

Page 196: ...e time difference measured in a single ended fashion at the midpoint of the transition of the true signal and the midpoint of the transition of the complement signal Differential input skew is limited primarily by DVICM such that at the given minimum output edge rate differential skew would cause a violation of DVICM before violating the output differential skew specification Figure 13 TIDIFF RX_C...

Page 197: ... the receiverís required input hold time HD is measured from the crossing point of the earliest RX_CAD transition to the RX_CLK transition crossing point THD accounts for receiver package skew distribution skew and device input hold time TSU and THD do not necessarily cover the required time to attain VID_MIN AC at the specified minimum input edge rates T In the following figure TSU MAX represents...

Page 198: ...inty composed of device output skew clock edge placement error and interconnect skew at the device inputs As such TCADVRS RH must be measured over a large number of samples and conditions which will maximize device output skew interconnect skew and clock edge placement error TCADVRS is measured from the crossing point of the last transitioning RX_CAD signal to the crossing point of the RX_CLK tran...

Page 199: ...ion Link Speed Min Max Units TODIFF Output Differential Skew 400 MT s 600 MT s 800 MT s 1000 MT s 1200 MT s 70 70 70 60 60 ps ps ps ps ps TIDIFF Input Differential Skew 400 MT s 600 MT s 800 MT s 1000 MT s 1200 MT s 695 467 345 280 234 1805 1200 905 720 600 ps ps ps ps ps TCADVRS Receiver input CADIN valid time to CLKIN 400 MT s 600 MT s 800 MT s 1000 MT s 1200 MT s 460 312 225 194 166 ps ps ps ps...

Page 200: ... MT s 800 MT s 1000 MT s 1200 MT s 460 312 225 194 166 ps ps ps ps ps TSU Receiver input setup time 400 MT s 600 MT s 800 MT s 1000 MT s 1200 MT s 0 0 0 0 0 250 215 175 153 138 ps ps ps ps ps THD Receiver input hold time 400 MT s 800 MT s 1200 MT s 0 0 0 250 175 138 ps ps ps Table 26 HyperTransport Link Transfer Timing Specifications Parameter Description Link Speed Min Max Units ...

Page 201: ...OD of the coupled transmission lines DRON pull up is the allowable difference in the driver output impedance between the true and complement when driving a logic ë0í and when driving a logic ë1í additionally defined as when true is driven high and when complement is driven high DRON pull up is defined to limit differences in both output rising edge slew rate and the resulting differential skew and...

Page 202: ... VLDT typ as a measurement condition Maxc c Maximum values assume VLDT VLDT max as a measurement condition Units VOD Differential output voltage 400 600 820 mV VOD Change in VOD Magnitude 75 75 mV VOCM Output common mode voltage 440 600 780 mV VOCM Change in VOCM magnitude 50 50 mV VID Input differential voltage 300 600 900 mV VID Change in VID magnitude 125 125 mV VICM Input common mode voltage 3...

Page 203: ...a a Minimum values assume VLDT VLDT min as a measurement condition Typb b Typical values assume VLDT VLDT typ as a measurement condition Maxc c Maximum values assume VLDT VLDT max as a measurement condition Units VOD Differential output voltage 495 600 715 mV Delta VOD Change in VOD Magnitude 15 15 mV VOCM Output common mode voltage 495 600 715 mV Delta VOCM Change in VOCM magnitude 15 15 mV VID I...

Page 204: ...5 Electrical Characteristics 204 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com 5 10 Reset Timing The following figure shows the reset timing of the Tsi308 ...

Page 205: ...5 Electrical Characteristics 205 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com Figure 18 Tsi308 Reset Timing ...

Page 206: ...ting Temperature Grade Temperature Commercial 0 to 70 ambient Table 31 Thermal Maximum Parameter Value Unit Die Temperature Maximum 125 C Maximum Power 7 W Table 32 Thermal Characteristics Parameter Symbol Package Air Flow Value Unit Thermal resistance junction to ambient JA 388 HSBGA 0 m s 13 2 C W 1 m s 12 0 2 m s 10 5 388 HSBGA w Heat Sinka a Recommended heat sink is Aavid 374524B00032 0 m s 9 ...

Page 207: ...his is 7 9 C W or less From Table 7 15 it can be seen that this thermal performance is possible by using the recommended Aavid 374524B00032 heat sink with 1 m s or greater air flow Applications with a lower ambient temperature and or less power dissipation may require less air flow and or no heat sink A spreadsheet to help determine the thermal requirements for a Tsi308 application is available up...

Page 208: ...ls 5 15 Supply Operatiing Ranges 5 16 Absolute Maximum Ratings Table 33 Supply Operating Ranges Parameter Minimum Typical Maximum Unit 3 3V 3 13 3 3 3 46 V 1 8V Analog PLL Power 1 71 1 8 1 89 V 1 8V Core Logic Power 1 71 1 8 1 89 V 1 2V 1 14 1 2 1 26 V Table 34 Absolute Maximum Ratings Parameter Minimum Typical Maximum Unit 3 3V 2 9 3 3 3 7 V 1 8V Analog PLL Power 1 6 1 8 2 0 V 1 8V Core Logic PLL...

Page 209: ...r Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com 6 Packaging This chapter discusses the following topics about Tsi308 s packaging Package Specification on page 210 Package Diagram on page 238 ...

Page 210: ...e Pin Name Pin CAVDD0 Y4 CAVDD1 G23 CAVSS0 W4 CAVSS1 H23 CORE_CLK_TEST A4 FATAL_ERR_N AF3 L_POWER_OK AF4 L_RST_N AE4 L0_CCLK_TESTa AA3 L0_DCLK_TEST AA4 L0_R50VLDT N2 L0_R50VSS N3 L0_RX_CAD_H 0 F3 L0_RX_CAD_H 1 F1 L0_RX_CAD_H 2 G3 L0_RX_CAD_H 3 H3 L0_RX_CAD_H 4 H1 L0_RX_CAD_H 5 K3 L0_RX_CAD_H 6 K1 L0_RX_CAD_H 7 M3 L0_RX_CAD_L 0 F2 L0_RX_CAD_L 1 G1 L0_RX_CAD_L 2 G2 L0_RX_CAD_L 3 H2 ...

Page 211: ... L0_RX_CTL_H M1 L0_RX_CTL_L N1 L0_TX_BYPASS_CLK AB2 L0_TX_CAD_H 0 AA2 L0_TX_CAD_H 1 Y3 L0_TX_CAD_H 2 AA1 L0_TX_CAD_H 3 V2 L0_TX_CAD_H 4 U2 L0_TX_CAD_H 5 U1 L0_TX_CAD_H 6 T2 L0_TX_CAD_H 7 R1 L0_TX_CAD_L 0 Y2 L0_TX_CAD_L 1 W3 L0_TX_CAD_L 2 Y1 L0_TX_CAD_L 3 V3 L0_TX_CAD_L 4 U3 L0_TX_CAD_L 5 T1 L0_TX_CAD_L 6 T3 L0_TX_CAD_L 7 P1 L0_TX_CLK_H W1 L0_TX_CLK_L V1 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 212: ...0 AA24 L1_RX_CAD_H 1 AA26 L1_RX_CAD_H 2 Y24 L1_RX_CAD_H 3 W24 L1_RX_CAD_H 4 W26 L1_RX_CAD_H 5 U24 L1_RX_CAD_H 6 U26 L1_RX_CAD_H 7 R24 L1_RX_CAD_L 0 AA25 L1_RX_CAD_L 1 Y26 L1_RX_CAD_L 2 Y25 L1_RX_CAD_L 3 W25 L1_RX_CAD_L 4 V26 L1_RX_CAD_L 5 U25 L1_RX_CAD_L 6 T26 L1_RX_CAD_L 7 R25 L1_RX_CLK_H V24 L1_RX_CLK_L V25 L1_RX_CTL_H R26 L1_RX_CTL_L P26 L1_TX_BYPASS_CLK E25 Table 35 Tsi308 Sorted by Name Pin N...

Page 213: ..._TX_CAD_H 5 K26 L1_TX_CAD_H 6 L25 L1_TX_CAD_H 7 M26 L1_TX_CAD_L 0 G25 L1_TX_CAD_L 1 H24 L1_TX_CAD_L 2 G26 L1_TX_CAD_L 3 J24 L1_TX_CAD_L 4 K24 L1_TX_CAD_L 5 L26 L1_TX_CAD_L 6 L24 L1_TX_CAD_L 7 N26 L1_TX_CLK_H H26 L1_TX_CLK_L J26 L1_TX_CTL_H N25 L1_TX_CTL_L N24 LDTSTOP_N AE3 NONFATAL_ERR_N AF2 P0_ACK64_N C19 P0_AD0 D5 P0_AD1 C5 P0_AD10 C8 P0_AD11 A8 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 214: ..._AD14 B9 P0_AD15 A9 P0_AD16 D10 P0_AD17 C10 P0_AD18 B10 P0_AD19 A10 P0_AD2 B5 P0_AD20 D11 P0_AD21 C11 P0_AD22 B11 P0_AD23 A11 P0_AD24 C12 P0_AD25 A12 P0_AD26 C13 P0_AD27 B13 P0_AD28 A13 P0_AD29 D14 P0_AD3 A5 P0_AD30 C14 P0_AD31 B14 P0_AD4 C6 P0_AD5 B6 P0_AD6 A6 P0_AD7 C7 P0_AD8 B7 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 215: ...E26 P0_BLK0_IRQ4 C26 P0_BLK1_IRQ0 C24 P0_BLK1_IRQ1 D26 P0_BLK1_IRQ2 C25 P0_BLK1_IRQ3 D24 P0_BLK1_IRQ4 B26 P0_BYPASS_E B3 P0_CBE0_N A14 P0_CBE1_N D15 P0_CBE2_N C15 P0_CBE3_N B15 P0_CLK C4 P0_DEVSEL_N A15 P0_FRAME_N C16 P0_GNT_IN_N B23 P0_GNT0_N B21 P0_GNT1_N A21 P0_GNT2_N D22 P0_GNT3_N C22 P0_GNT4_N B22 P0_GNT5_N A22 P0_IRDY_N A16 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 216: ...P0_PAR64 A18 P0_PCIX_133_N B24 P0_PCIX_N A24 P0_PERR_N C18 P0_REQ_OUT_N C23 P0_REQ0_N B19 P0_REQ1_N A19 P0_REQ2_N C20 P0_REQ3_N A20 P0_REQ4_N D21 P0_REQ5_N C21 P0_REQ64_N D19 P0_RST_N C2 P0_SERR_N D18 P0_STOP_N B17 P0_TRDY_N C17 P0_TSTCLK E4 P0_TSTDI F4 P0_TSTDIO E3 P0_TSTDO E2 P0_TSTMOD0 E1 P0_TSTMOD1 D3 P0_TSTMS D2 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 217: ... AC18 P1_AD12 AD18 P1_AD13 AE18 P1_AD14 AF18 P1_AD15 AC17 P1_AD16 AD17 P1_AD17 AE17 P1_AD18 AF17 P1_AD19 AC16 P1_AD2 AD21 P1_AD20 AD16 P1_AD21 AE16 P1_AD22 AF16 P1_AD23 AD15 P1_AD24 AF15 P1_AD25 AD14 P1_AD26 AE14 P1_AD27 AF14 P1_AD28 AC13 P1_AD29 AD13 P1_AD3 AE21 P1_AD30 AE13 P1_AD31 AF13 P1_AD4 AF21 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 218: ..._BLK0_IRQ1 AF24 P1_BLK0_IRQ2 AE24 P1_BLK0_IRQ3 AD23 P1_BLK0_IRQ4 AF25 P1_BLK1_IRQ0 AA23 P1_BLK1_IRQ1 AD26 P1_BLK1_IRQ2 AD25 P1_BLK1_IRQ3 AD24 P1_BLK1_IRQ4 AC24 P1_BYPASS_E AD3 P1_CBE0_N AC12 P1_CBE1_N AD12 P1_CBE2_N AE12 P1_CBE3_N AF12 P1_CLK AD22 P1_DEVSEL_N AD11 P1_FRAME_N AF11 P1_GNT_IN_N AF5 P1_GNT0_N AC6 P1_GNT1_N AD6 P1_GNT2_N AE6 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 219: ...N AC9 P1_M66EN AB26 P1_OIR_DISCON_EVENT AB23 P1_PAR AF9 P1_PCIX_133_N AC25 P1_PCIX_N AC26 P1_PERR_N AE9 P1_REQ_OUT_N AE5 P1_REQ0_N AC8 P1_REQ1_N AD8 P1_REQ2_N AE8 P1_REQ3_N AF8 P1_REQ4_N AD7 P1_REQ5_N AF7 P1_RST_N AE23 P1_SERR_N AD9 P1_STOP_N AF10 P1_TRDY_N AE10 PAVDD0 D6 PAVDD1 AC22 PAVSS0 D7 PAVSS1 AC21 PCIA_CLK_TEST B4 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 220: ...B_CLK_TESTb AF23 PLL_SEL_BK AC2 PLL_SELDIV2 AC1 PLL_TESTENB AB1 SCAN_EN AB3 SROM_SCK D1 SROM_SDA C1 TCK AD4 TDI AD2 TDO AE1 TMODE AC3 TMS AB25 TRST_N AB24 TX_BYPASS_CLK_E AD1 a Multiplexed pin see Table 37 on page 232 b Multiplexed pin see Table 37 on page 232 Table 35 Tsi308 Sorted by Name Pin Name Pin ...

Page 221: ...Number Pin Pin Name A3 P0_OIR_DISCON_EVENT A4 CORE_CLK_TEST A5 P0_AD3 A6 P0_AD6 A7 P0_AD9 A8 P0_AD11 A9 P0_AD15 A10 P0_AD19 A11 P0_AD23 A12 P0_AD25 A13 P0_AD28 A14 P0_CBE0_N A15 P0_DEVSEL_N A16 P0_IRDY_N A17 P0_LOCK_N A18 P0_PAR64 A19 P0_REQ1_N A20 P0_REQ3_N A21 P0_GNT1_N A22 P0_GNT5_N A23 P0_M66EN A24 P0_PCIX_N B3 P0_BYPASS_E B4 PCIA_CLK_TEST B5 P0_AD2 ...

Page 222: ...AD18 B11 P0_AD22 B13 P0_AD27 B14 P0_AD31 B15 P0_CBE3_N B17 P0_STOP_N B18 P0_PAR B19 P0_REQ0_N B21 P0_GNT0_N B22 P0_GNT4_N B23 P0_GNT_IN_N B24 P0_PCIX_133_N B26 P0_BLK1_IRQ4 C1 SROM_SDA C2 P0_RST_N C4 P0_CLK C5 P0_AD1 C6 P0_AD4 C7 P0_AD7 C8 P0_AD10 C9 P0_AD13 C10 P0_AD17 C11 P0_AD21 C12 P0_AD24 Table 36 Tsi308 Sorted by Number Pin Pin Name ...

Page 223: ...17 P0_TRDY_N C18 P0_PERR_N C19 P0_ACK64_N C20 P0_REQ2_N C21 P0_REQ5_N C22 P0_GNT3_N C23 P0_REQ_OUT_N C24 P0_BLK1_IRQ0 C25 P0_BLK1_IRQ2 C26 P0_BLK0_IRQ4 D1 SROM_SCK D2 P0_TSTMS D3 P0_TSTMOD1 D5 P0_AD0 D6 PAVDD0 D7 PAVSS0 D9 P0_AD12 D10 P0_AD16 D11 P0_AD20 D14 P0_AD29 D15 P0_CBE1_N D18 P0_SERR_N D19 P0_REQ64_N Table 36 Tsi308 Sorted by Number Pin Pin Name ...

Page 224: ...OD0 E2 P0_TSTDO E3 P0_TSTDIO E4 P0_TSTCLK E23 P0_BLK0_IRQ0 E24 P0_BLK0_IRQ1 E25 L1_TX_BYPASS_CLK E26 P0_BLK0_IRQ3 F1 L0_RX_CAD_H 1 F2 L0_RX_CAD_L 0 F3 L0_RX_CAD_H 0 F4 P0_TSTDI F23 L1_CCLK_TESTa F24 L1_DCLK_TEST F25 L1_TX_CAD_H 0 F26 L1_TX_CAD_H 2 G1 L0_RX_CAD_L 1 G2 L0_RX_CAD_L 2 G3 L0_RX_CAD_H 2 G23 CAVDD1 G24 L1_TX_CAD_H 1 G25 L1_TX_CAD_L 0 Table 36 Tsi308 Sorted by Number Pin Pin Name ...

Page 225: ...6 L1_TX_CLK_H J1 L0_RX_CAD_L 4 J2 L0_RX_CLK_L J3 L0_RX_CLK_H J24 L1_TX_CAD_L 3 J25 L1_TX_CAD_H 3 J26 L1_TX_CLK_L K1 L0_RX_CAD_H 6 K2 L0_RX_CAD_L 5 K3 L0_RX_CAD_H 5 K24 L1_TX_CAD_L 4 K25 L1_TX_CAD_H 4 K26 L1_TX_CAD_H 5 L1 L0_RX_CAD_L 6 L24 L1_TX_CAD_L 6 L25 L1_TX_CAD_H 6 L26 L1_TX_CAD_L 5 M1 L0_RX_CTL_H M2 L0_RX_CAD_L 7 M3 L0_RX_CAD_H 7 M26 L1_TX_CAD_H 7 Table 36 Tsi308 Sorted by Number Pin Pin Nam...

Page 226: ...1 L0_TX_CAD_L 7 P2 L0_TX_CTL_H P3 L0_TX_CTL_L P24 L1_R50VSS P25 L1_R50VLDT P26 L1_RX_CTL_L R1 L0_TX_CAD_H 7 R24 L1_RX_CAD_H 7 R25 L1_RX_CAD_L 7 R26 L1_RX_CTL_H T1 L0_TX_CAD_L 5 T2 L0_TX_CAD_H 6 T3 L0_TX_CAD_L 6 T26 L1_RX_CAD_L 6 U1 L0_TX_CAD_H 5 U2 L0_TX_CAD_H 4 U3 L0_TX_CAD_L 4 U24 L1_RX_CAD_H 5 U25 L1_RX_CAD_L 5 U26 L1_RX_CAD_H 6 V1 L0_TX_CLK_L Table 36 Tsi308 Sorted by Number Pin Pin Name ...

Page 227: ...3 L0_TX_CAD_L 1 W4 CAVSS0 W24 L1_RX_CAD_H 3 W25 L1_RX_CAD_L 3 W26 L1_RX_CAD_H 4 Y1 L0_TX_CAD_L 2 Y2 L0_TX_CAD_L 0 Y3 L0_TX_CAD_H 1 Y4 CAVDD0 Y24 L1_RX_CAD_H 2 Y25 L1_RX_CAD_L 2 Y26 L1_RX_CAD_L 1 AA1 L0_TX_CAD_H 2 AA2 L0_TX_CAD_H 0 AA3 L0_CCLK_TESTb AA4 L0_DCLK_TEST AA23 P1_BLK1_IRQ0 AA24 L1_RX_CAD_H 0 AA25 L1_RX_CAD_L 0 AA26 L1_RX_CAD_H 1 AB1 PLL_TESTENB Table 36 Tsi308 Sorted by Number Pin Pin Na...

Page 228: ..._N AB25 TMS AB26 P1_M66EN AC1 PLL_SELDIV2c AC2 PLL_SEL_BK AC3 TMODE AC5 P1_GNT4_N AC6 P1_GNT0_N AC8 P1_REQ0_N AC9 P1_LOCK_N AC12 P1_CBE0_N AC13 P1_AD28 AC16 P1_AD19 AC17 P1_AD15 AC18 P1_AD11 AC20 P1_AD5 AC21 PAVSS1 AC22 PAVDD1 AC24 P1_BLK1_IRQ4 AC25 P1_PCIX_133_N AC26 P1_PCIX_N AD1 TX_BYPASS_CLK_E AD2 TDI AD3 P1_BYPASS_E Table 36 Tsi308 Sorted by Number Pin Pin Name ...

Page 229: ...Q1_N AD9 P1_SERR_N AD10 P1_IRDY_N AD11 P1_DEVSEL_N AD12 P1_CBE1_N AD13 P1_AD29 AD14 P1_AD25 AD15 P1_AD23 AD16 P1_AD20 AD17 P1_AD16 AD18 P1_AD12 AD19 P1_AD9 AD20 P1_AD6 AD21 P1_AD2 AD22 P1_CLK AD23 P1_BLK0_IRQ3 AD24 P1_BLK1_IRQ3 AD25 P1_BLK1_IRQ2 AD26 P1_BLK1_IRQ1 AE1 TDO AE3 LDTSTOP_N AE4 L_RST_N AE5 P1_REQ_OUT_N Table 36 Tsi308 Sorted by Number Pin Pin Name ...

Page 230: ...BE2_N AE13 P1_AD30 AE14 P1_AD26 AE16 P1_AD21 AE17 P1_AD17 AE18 P1_AD13 AE20 P1_AD7 AE21 P1_AD3 AE22 P1_AD0 AE23 P1_RST_N AE24 P1_BLK0_IRQ2 AE26 P1_BLK0_IRQ0 AF2 NONFATAL_ERR_N AF3 FATAL_ERR_N AF4 L_POWER_OK AF5 P1_GNT_IN_N AF6 P1_GNT3_N AF7 P1_REQ5_N AF8 P1_REQ3_N AF9 P1_PAR AF10 P1_STOP_N AF11 P1_FRAME_N AF12 P1_CBE3_N Table 36 Tsi308 Sorted by Number Pin Pin Name ...

Page 231: ...22 AF17 P1_AD18 AF18 P1_AD14 AF19 P1_AD10 AF20 P1_AD8 AF21 P1_AD4 AF22 P1_AD1 AF23 PCIB_CLK_TESTd AF24 P1_BLK0_IRQ1 AF25 P1_BLK0_IRQ4 a Multiplexed pin see Table 37 on page 232 b Multiplexed pin seeTable 37 on page 232 c Multiplexed pin see Table 37 on page 232 d Multiplexed pin see Table 37 on page 232 Table 36 Tsi308 Sorted by Number Pin Pin Name ...

Page 232: ...7 Tsi308 Multiplexed Pins Pin Default Pin Name Multiplexed Pin Name Multiplex Select Pin F23 L1_CCLK_TEST P1_TSTMS PLL_TESTENB F24 L1_DCLK_TEST P1_TSTMOD1 PLL_TESTENB AA3 L0_CCLK_TEST P1_TSTDIO PLL_TESTENB AA4 L0_DCLK_TEST P1_TSTDI PLL_TESTENB AC1 PLL_SELDIV2 P1_TSTCLK PLL_TESTENB AC2 PLL_SEL_BK P1_TSTMOD0 PLL_TESTENB AD1 TX_BYPASS_CLK_E P1_TSTDO PLL_TESTENB AF23 PCIB_CLK_TEST SCAN_CLK PLL_TESTENB...

Page 233: ...tion www tundra com 6 1 4 2 1 8V Core Power Pins Table 39 Tsi308 1 8V Core Power Pin Pin Name D17 VDD H25 VDD J4 VDD L2 VDD L11 VDD L12 VDD L15 VDD L16 VDD M11 VDD M12 VDD M15 VDD M16 VDD M23 VDD R4 VDD R11 VDD R12 VDD R15 VDD R16 VDD T11 VDD T12 VDD T15 VDD T16 VDD T25 VDD V23 VDD ...

Page 234: ...Pin Type Y4 CAVDD0 1 8V PLL Power G23 CAVDD1 1 8V PLL Power D6 PAVDD0 1 8V PLL Power AC22 PAVDD1 1 8V PLL Power A4 PAVDD2 1 8V PLL Power W4 CAVSS0 PLL Ground H23 CAVSS1 PLL Ground D7 PAVSS0 PLL Ground AC21 PAVSS1 PLL Ground B4 PAVSS2 PLL Ground Table 41 Tsi308 3 3V PCI Core and I O Power and HT Receive Power Pin Pin Name B8 VCC3V3 VDDIO VDDIOA B12 VCC3V3 VDDIO VDDIOA B16 VCC3V3 VDDIO VDDIOA B20 VC...

Page 235: ...4 VCC3V3 VDDIO VDDIOA L3 VCC3V3 VDDIO VDDIOA T24 VCC3V3 VDDIO VDDIOA U23 VCC3V3 VDDIO VDDIOA Y23 VCC3V3 VDDIO VDDIOA AC4 VCC3V3 VDDIO VDDIOA AC7 VCC3V3 VDDIO VDDIOA AC11 VCC3V3 VDDIO VDDIOA AC15 VCC3V3 VDDIO VDDIOA AC19 VCC3V3 VDDIO VDDIOA AC23 VCC3V3 VDDIO VDDIOA AE2 VCC3V3 VDDIO VDDIOA AE7 VCC3V3 VDDIO VDDIOA AE11 VCC3V3 VDDIO VDDIOA AE15 VCC3V3 VDDIO VDDIOA AE19 VCC3V3 VDDIO VDDIOA AE25 VCC3V3 ...

Page 236: ...or 1 2V HyperTransport power 1 8V core power and 3 3V PCI and HT receive power The PLL ground pins are listed in Section 6 1 4 3 on page 234 Table 42 Tsi308 Ground Pins Pin Pin Name A1 VSS A26 VSS D13 VSS H4 VSS L4 VSS L13 VSS L14 VSS L23 VSS M4 VSS M13 VSS M14 VSS M25 VSS N4 VSS N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS P11 VSS P12 VSS P13 VSS P14 VSS ...

Page 237: ...anual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com P15 VSS P16 VSS P23 VSS R2 VSS R13 VSS R14 VSS R23 VSS T4 VSS T13 VSS T14 VSS T23 VSS W23 VSS AC14 VSS AF1 VSS AF26 VSS Table 42 Tsi308 Ground Pins Pin Pin Name ...

Page 238: ...ts may be stored in unopened vacuum packed antistatic bag up to a minimum of 12 months at 40 C and 90 humidity Parts may be stored outside of bag indefinitely at 20 humidity Floor Life Packages will absorb moisture after opening the bag Parts must be mounted on PCB within 48 hours after bag is opened otherwise baking is required Floor life conditions are 30 C and 60 humidity Baking Time 12 hours 1...

Page 239: ...d corresponding OIR_DISCON_EVENT gets asserted The design requirement for the PCI X card is such that OIR_DISCON_EVENT signal is asserted first and then after few milli seconds the PCI X card can be disconnected 4 Tsi308 completes the ongoing transaction on the PCI port Tsi308 asserts the REQ to prevent other PCI masters from taking the bus No further transactions happen on the PCI bus 5 All the s...

Page 240: ... PCI X modes are 50 66 100 and 133 MHz However the PCI frequencies can be adjusted to any value between the standard frequencies for each mode Refer definitions for bits 3 2 in section 5 4 1 89 for CSR values their corresponding PCI frequency ranges and when to program these values 11 PCI PLL is allowed to lock to the new frequency PCI PLL takes about 5ms to lock 12 After the PCI PLL s are locked ...

Page 241: ...ndations for Use 8 1 1 Unused HyperTransport CAD CLK and CTL Inputs If using only one of the two available HyperTransport link interfaces then the unused Lx_RX_CAD 7 0 Lx_CLK inputs must be pulled to their logic low levels This means that Lx_CAD x _L must be pulled high and Lx_CAD x _H must be pulled low A 50Ω pull up pull down resistor value is recommended as this will hold Lx_CAD x _L at 0 9V an...

Page 242: ... the AS90L10208 on board PLLs it is important to provide adequate power filtering for the dedicated PLL power pins listed in 8 3 3 The recommended power filtering for each of the PLL power pins is a series ferrite bead followed by a low ESR 10 μF capacitor and a 0 1 μF ceramic capacitor to GND A diagram is shown in Figure 22 Each PLL power pin should have its own filter Figure 22 Recommended PLL P...

Page 243: ...yout Guidelines The Tsi308 is a PCI PCI X to HyperTransport bridge that also acts as a HyperTransport tunnel This layout guide focuses on the HyperTransport interface only The AS90L10208 conforms to draft 1 05 of the HyperTransport specification HyperTransport is a parallel unidirectional protocol with differential DDR signaling on both the transmit and receive interfaces The AS90L10208 supports l...

Page 244: ...s laid out in the Interface Design Guide for end to end trace length variations between different signals When using trace by trace compensated matching the system board trace length must compensate for the mismatch in the package trace lengths on a trace by trace basis Effectively the length of the system board trace must be lengthened or shortened to compensate for short or long traces on the tr...

Page 245: ...ion www tundra com The die pad to ball trace length data for the AS90L10208 is included in the AS90L10208 die pad to ball trace length information at the end of this document Similar information for other devices that interface to the AS90L10208 should be available from the respective vendors ...

Page 246: ...e vias for the bottom layer Decoupling is required in the vicinity of a layer change Routing is to be 20 5 5 5 20 mils for all HyperTransport nets Route 50 5 5 5 50 mils when serpentining where the 50 mil clearance is any net to itself Group electrical lengths are matched piecewise 8 2 3 AS90L10208 Board Trace Electrical Specification VLDT 1 2 V 60 mV Maximum RDC 0 29 Ω in Maximum RAC 1 50 Ω in 1 ...

Page 247: ...he ZOD is the governing factor Each true signal is routed to within 25 mils of its compliment Table 43 System Board Design Rules Description Definition Parameter Rules 1 H to L trace length matching differential skew using trace by trace compensation Defines the absolute length difference allowed between H and L signal traces Parameter DiffPCBskew 400 to 800 MT s 20 ps 800 MT s 5 ps Link speed Mic...

Page 248: ...133 111 1200 MT s 100 84 1600 MT s 67 34 4 CAD CTL to CAD CTL trace length matching group skew Defines the length difference allowed between the longest and shortest average of H and L for all CAD CTL signals within a clock group Parameter TPCBskewcad Link speed Microstrip Stripline 400 MT s 667 555 600 MT s 667 555 800 MT s 400 333 1000 MT s 266 222 1200 MT s 200 167 1600 MT s 133 111 6 CAD CTL C...

Page 249: ... for bus speeds 400 Mb s with the exception of vias for breakout under the package If a clock data group must change layers place a pair s vias as close as possible in order to prevent a major ZOD discontinuity It is all right for the via anti pad plane clearances to overlap in this instance If a clock data group is split between top and bottom routing layers trace length must be inserted on the t...

Page 250: ...ach port and that power is supplied from a dedicated island for each VLDT in the power plane Detailed information on VLDT layout is provided in the following sections 8 3 1 Number of Layers The number of layers on the board dictates if VLDT is routed on the board as a trace or as section of a plane A larger number of layers alleviates some of the signal routing constraints allowing for placing a g...

Page 251: ...r better OsCon or aluminum polymer type capacitors be used for bulk decoupling 8 3 5 Multiple HyperTransport Links A single VLDT regulator can be used to supply power to two HyperTransport links The distance from the regulator to the AS90L10208 package should not exceed 1 5 to 2 0 inches This scheme is recommended only for applications where board space is constrained so much that it is impossible...

Page 252: ... R1 L0_TX_CAD_H 7 9 665 0 3805 96 65 P1 L0_TX_CAD_L 7 9 660 0 3803 96 60 T2 L0_TX_CAD_H 6 8 198 0 3227 81 98 T3 L0_TX_CAD_L 6 8 342 0 3284 83 42 U1 L0_TX_CAD_H 5 10 041 0 3953 100 41 T1 L0_TX_CAD_L 5 10 004 0 3939 100 04 U2 L0_TX_CAD_H 4 8 915 0 3510 89 15 U3 L0_TX_CAD_L 4 8 861 0 3489 88 61 V2 L0_TX_CAD_H 3 8 847 0 3483 88 47 V3 L0_TX_CAD_L 3 8 607 0 3389 86 07 AA1 L0_TX_CAD_H 2 11 856 0 4668 118...

Page 253: ...91 G1 L0_RX_CAD_L 1 11 751 0 4627 117 51 F3 L0_RX_CAD_H 0 9 897 0 3897 98 97 F2 L0_RX_CAD_L 0 9 910 0 3902 99 10 J3 L0_RX_CLK_H 8 242 0 3245 82 42 J2 L0_RX_CLK_L 8 293 0 3265 82 93 M1 L0_RX_CTL_H 8 785 0 3459 87 85 N1 L0_RX_CTL_L 8 715 0 3431 87 15 M26 L1_TX_CAD_H 7 9 720 0 3827 97 20 N26 L1_TX_CAD_L 7 9 809 0 3862 98 09 L25 L1_TX_CAD_H 6 8 286 0 3262 82 86 L24 L1_TX_CAD_L 6 8 199 0 3228 81 99 K26...

Page 254: ... L1_TX_CTL_L 7 719 0 3039 77 19 R24 L1_RX_CAD_H 7 7 636 0 3006 76 36 R25 L1_RX_CAD_L 7 8 136 0 3203 81 36 U26 L1_RX_CAD_H 6 10 046 0 3955 100 46 T26 L1_RX_CAD_L 6 9 933 0 3911 99 33 U24 L1_RX_CAD_H 5 8 778 0 3456 87 78 U25 L1_RX_CAD_L 5 8 865 0 3490 88 65 W26 L1_RX_CAD_H 4 10 925 0 4301 109 25 V26 L1_RX_CAD_L 4 10 742 0 4229 107 42 W24 L1_RX_CAD_H 3 8 886 0 3499 88 86 W25 L1_RX_CAD_L 3 8 828 0 347...

Page 255: ...pedance if a 5 mil wide trace is used with 5 mil spacing on any signal layer AA24 L1_RX_CAD_H 0 10 029 0 3948 100 29 AA25 L1_RX_CAD_L 0 9 797 0 3857 97 97 V24 L1_RX_CLK_H 8 544 0 3364 85 44 V25 L1_RX_CLK_L 8 587 0 3381 85 87 R26 L1_RX_CTL_H 9 514 0 3746 95 14 P26 L1_RX_CTL_L 9 356 0 3684 93 56 Table 44 Pad to Ball Trace Length Information Ball number Signal Name Pad to Ball Trace Length mm Pad to ...

Page 256: ... 5 mil nominal trace width on both internal and external layers 2 Impedance is nominally 60Ω with the dielectrics shown All internal signal layers are oz copper 3 All internal reference planes are 1 oz copper 4 Overall board thickness is 91 6 mils measured between outer resin surfaces 1 2 3 4 5 6 7 8 9 10 11 12 GND 2 5V 5V GND 3 3V GND GND 5 8 8 8 8 8 8 8 8 8 5 Recommended Stackup With Single Stri...

Page 257: ...or Corporation www tundra com 9 Ordering Information The following table contains ordering information for the Tsi308 Table 45 Ordering Information Part Number Temperature Package Pin Count Tsi308 600CE Commercial BGA 388 Tsi308 600CEV Commercial BGA RoHS 388 ...

Page 258: ...9 Ordering Information 258 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

Page 259: ...ex A absolute maximum ratings 208 AC test conditions 202 AC timing definitions 190 D document conventions document status 19 numeric conventions 18 symbols 18 H HT transmit clock parameters 201 P package types 257 packaging 209 pin count 257 S SROM timing 201 T temperature 257 timing SROM 201 ...

Page 260: ...Index 260 Tsi308 User Manual 80D4000_MA001_02 Tundra Semiconductor Corporation www tundra com ...

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