Tundra TSI308, User Manual

Page: 119 / 260

4. Register Descriptions 119
Tsi308 User Manual
80D4000_MA001_02
Tundra Semiconductor Corporation
www.tundra.com
4.3.5.34 HyperTransport Capability ID Register
Register Offset : 40h
0 R/W 0 SP/DSP:
Parity Error Response Enable:
Enables parity errors to be reported by P_PERR_N, FATAL_ERR_N or
NONFATAL_ERR_N error interrupt.
Not persistent through warm reset.
GSP/ GDP:
Data Error Response Enable:
This bit must be set to allow Tsi308 to set the Master Data Error bit of the Secondary
Status register.
In addition setting this bit enables Tsi308 to forward address and data parity errors
from secondary interface onto the primary interface as follows:
Address Parity Error:
When Tsi308 detects an address parity error on its secondary interface it takes the
following actions:
Floods its both outgoing links with sync packets if SERR# Enable bit in the
Command register is set.
Sets Parity Error Detected bit in its secondary status register.
Sets SERR Signaled bit of the status register.
If Tsi308 has claimed the cycle and terminated it by signaling a Target-Abort then
Signaled Target Abort bit in its secondary status register is also set.
Data Parity Error:
If Tsi308 detects data parity error when it is the master of a transaction on its
secondary interface it sets Master Data Error bit in the Secondary Status register.
If Tsi308 detects data parity error when it is the target of a transaction on its
secondary interface it sets Parity Error Detected bit in the Secondary Status register.
In both cases Tsi308 forwards the data parity error onto primary interface by setting
Data Error bit in the request or response packets.
Bit
R/W
Access
Initial
Value
Field Name and Description
7:0 R 08h Id:
HyperTransport Capability ID assigned by the PCI SIG.
Bit
R/W
Access
Initial
Value
Field Name and Description