Tundra TSI308, User Manual

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4. Register Descriptions 186
Tsi308 User Manual
80D4000_MA001_02
Tundra Semiconductor Corporation
www.tundra.com
4.3.7.7 INTERRUPT Definition Registers
1Fh 31:0 R/W 0h INTR7[63:32]
20h 31:0 R/W 0h INTR8[31:0]
21h 31:0 R/W 0h INTR8[63:32]
22h 31:0 R/W 0h INTR9[31:0]
23h 31:0 R/W 0h INTR9[63:32]
3Fh-24h R 0h Reserved
Bit R/W Access Initial Value Field Name and Description
63:56 R/W 0h Intr Info[15:8] Destination
55:32 R/W 0h Intr Info[55:32] Extended Destination: If a device does not support 32-bit
destinations, this field is read-only 0.
31:17 R/O 0h Reserved
16 R/W 1h Mask: When this bit is set, the interrupt is masked.
15 R/W 0h Intr Info[5] Request EOI: If set, after each interrupt request is sent the
device waits for the Waiting for EOI bit to be cleared before sending
another interrupt
14 R/O 0h Waiting for EOI: If RQEOI is 1, then this bit is set by hardware when an
interrupt request is sent and cleared by hardware when the EOI is returned.
13 R/W 0h Polarity: For external interrupt sources, when this bit is set, the interrupt
signal is active-low. If clear, the interrupt signal is active-high. For internal
interrupt sources, this bit is reserved.
12 R/O 0h Reserved
11 R/W 0h Intr Info[6] Destination Mode: 0 = Physical, 1 = Logical
10:8 R/W 0h Intr Info[4:2] Message Type[2:0]
7:0 R/W 0h Intr Info[23:16] Vector
Address
Offset Bit
R/W
Access
Initial
Value
Field Name and Description