Tundra TSI308, User Manual

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3. Clock Frequency and Mode Selection Hardware Straps 73
Tsi308 User Manual
80D4000_MA001_02
Tundra Semiconductor Corporation
www.tundra.com
For debug and test purposes, the Tsi308 allows bypassing of HT PLLs. It provides separate
bypass clock inputs to both the HT links. All bypass clocks must be derived from the same base
frequency source. The PCI_A ,PCI_B and core PLLs also can be bypassed. When PCI PLLs
are bypassed PCI_A interface is run directly at P0_CLK and PCI_B interface is run directly at
P1_CLK. When CORE PLL is bypassed, core runs directly at REFCLK_C in ‘RevC mode’ and
runs directly at P0_CLK at other modes.
Following sections describe the strap options.
3.2 Core Clock Frequency Selection in RevC mode
All the inputs to Core PLL are taken from the straps. These strap values are taken during cold
reset period.
Table 13 shows the valid strap combinations for Core PLL.
For all the straps that use P0_AD bus, logic 1 assumes that the signal is pulled high
to 3.3v supply through a 4.7k ohm resister and logic 0 assumes that the signal is
pulled low to ground through a 4.7k ohm resister.
Table 13: Core Clock Frequency Selection Straps in RevC mode
P0_AD[23,22,21,20] REFCLK_C (MHz) Core Clock (MHz)
0001 25 100
0010 25 200
0011 33 133
0100 33 200
0101 50 100
0110 50 200
0111 66 133
1000 66 200
1001 100 200
1010 133 200
All other values are reserved