Tundra TSI308, User Manual

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2. Interface Operation 38
Tsi308 User Manual
80D4000_MA001_02
Tundra Semiconductor Corporation
www.tundra.com
Packet transmission is paced by the transmit buffer counters maintained in each virtual channel
for both command/address and data, as the HyperTransport specification describes. These
counters are decremented as packets are transmitted and incremented as buffer release messages
are received from the transmitter at the link’s other end. Transmit buffer counters can be
throttled using the Transmit Buffer Counter Maximum CSRs (C8h and CCh).
2.2.4.1 Packet Insertion
To prevent devices close to the host bridge from starving devices further out in the chain of
bandwidth, the Tsi308 implements the packet insertion fairness algorithm described in [1]. This
algorithm throttles the insertion rate of packets from Tsi308 relative to packets being forwarded
and attempts to balance the packet insertion rates of all devices on the chain.
Insertion of buffer release messages is forced, even when the outgoing transmission stream is
busy. Forcing allows traffic to flow through the Tsi308 continuously while maintaining a
relatively small number of Rx buffers. The Tsi308 forces a buffer release message as soon as
possible when an Rx buffer is freed, subject to the requirements of the HyperTransport protocol.
The frequency of buffer release messages is limited under HyperTransport Transmit Control
CSR (6Eh) to prevent them from occupying too much bandwidth in a busy stream. Throttling
buffer releases clumps the released messages together and raises their efficiency.
In a single-hosted HyperTransport chain, the Tsi308 may be at the end of the chain furthest from
the host and therefore have no downstream link connection. In this case, packets are routed to
the End of Chain (EOC) logic in the unconnected link interface. The EOC logic drops responses
and posted requests and generates Non-Existent Access (NXA) Error responses back into the
receiver for non-posted requests. These error responses then get forwarded back to the other
HyperTransport link interface’s reflect path Rx buffers and back to the requesting device. Error
logging for the dropped packets occurs in the Link Control Registers CSRs (44h and 48h) in
Tsi301 mode or in the Link Error Register (4Dh and 51h) in standard HyperTransport mode.
2.3 Outbound Transactions
Outbound transactions to the Tsi308 are those accepted from the HyperTransport chain. All
outbound requests go first from the HyperTransport link interface on which they are received to
the Outbound Request Controller (ORC). This controller is responsible for issuing the request to
the appropriate destination functional unit and for tracking the request state while it is
outstanding.
When Tsi308 is operating in Dual Device Mode(Split PCI-X Bus), fairness is
implemented on cumulative basis wherein insert rate is computed for a single device
in standard way and then actual insertion rate is doubled to account for two devices
in single node/chip.