Control Registers and RAM
94
Bit 13
NOBRK.
non-interleaved DMA block transfer.
1 =
NOBRK ensures that 1 data transfers are performed from
the buffer referenced by BUFID without a data transfer from any other
buffer. The sequencer remains at the DMA buffer until 1
transfers have been processed.
This can be used to generate a burst transfer to one device without dis-
abling the chip select signal in-between (the concerned buffer has to
be configured with CSHOLD=1). Another example would be to have a
defined block data transfer in slave mode, synchronous to the master
SPI.
Triggering of higher prior transfer groups or enabling of higher prior
DMA channels is not able to interrupt NOBRK block transfer.
0 =
The DMA transfers through the buffer referenced by BUFID are inter-
leaved by data transfers from other active buffers or transfer groups.
Every time the sequencer checks the DMA buffer it performs one trans-
fer and then steps to the next buffer.
Bits 12:8
ICOUNT.
Initial number of DMA transfers
ICOUNT[4:0] is used to preset the transfer counter COUNT[4:0]. Every time
COUNT[4:0] hits zero it is reloaded with ICOUNT[4:0]. The real number of
transfer equals ICOUNT[4:0] plus one.
If ONESHOT is set, ICOUNT[4:0] defines the number of DMA transfers that
are performed before the MibSPI automatically disables the DMA channels.
If NOBRK is set, ICOUNT[4:0] defines the number of DMA transfers that are
performed in one sequence without a transfer from any other buffer.
Bits 7:5
Reserved.
Bits 4:0
COUNT.
Actual number of remaining DMA transfer
COUNT[4:0] is a read-only bit field. It comprises the actual number of DMA
transfers that remain, until the DMA channel is disabled if ONESHOT is set.
Note:
In the case of TX and RX DMA request are enabled, the COUNT register will
be decremented when RX has been serviced.
Summary of Contents for TMS470R1x
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