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Control Registers and RAM
78
7.22
Transfer Group Interrupt Level Register (TGINTLVL)
The register TGINTLVL comprises the transfer group interrupt level flags for
“transfer finished” event and for “transfer suspended” event. With each of the
flags the corresponding interrupt can be mapped to either INT0 interrupt line
or INT1 interrupt line.
The number of implemented transfer groups is dependent on the MibSPI
macro-cell. Each of the level bits in the higher half-word and the lower half-
word of TGINTLVL belongs to one transfer group. In below register map a
super-set MibSPI with 16 transfer groups is assumed. The real number of
interrupt level bits depends on the implemented number of transfer groups.
Bits 31:16
INTLVLRDYx.
Transfer group interrupt level for “transfer finished” event.
1 =
A transfer finished interrupt of the transfer group x is mapped to inter-
rupt line INT1.
0 =
A transfer finished interrupt of the transfer group x is mapped to inter-
rupt line INT0.
Bits 15:0
INTLVLSUSx.
Transfer group interrupt level for “transfer suspended” event.
1 =
A transfer suspended interrupt of the transfer group x is mapped to
interrupt line INT1.
0 =
A transfer suspended interrupt of the transfer group x is mapped to
interrupt line INT0.
Bits
31
30
29
28
27
26
25
24
060h
INTLVL
RDY15
INTLVL
RDY14
INTLVL
RDY13
INTLVL
RDY12
INTLVL
RDY11
INTLVL
RDY10
INTLVL
RDY9
INTLVL
RDY8
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Bits
23
22
21
20
19
18
17
16
INTLVLRDY7 INTLVLRDY6 INTLVLRDY5 INTLVLRDY4 INTLVLRDY3 INTLVLRDY2 INTLVLRDY1 INTLVLRDY0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Bits
15
14
13
12
11
10
9
8
INTLVL
SUS15
INTLVL
SUS14
INTLVL
SUS13
INTLVL
SUS12
INTLVL
SUS11
INTLVL
SUS10
INTLVL
SUS9
INTLVL
SUS8
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Bits
7
6
5
4
3
2
1
0
INTLVLSUS7 INTLVLSUS6 INTLVLSUS5 INTLVLSUS4 INTLVLSUS3 INTLVLSUS2 INTLVLSUS1 INTLVLSUS0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Legend: R = Read, W = Write, C = Clear, U = Undefined,
-n
= Value after reset, x = indeterminate
Summary of Contents for TMS470R1x
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