DMA Interface
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
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6
DMA Interface
If handling the MibSPI message traffic on a character-by-character basis
requires too much CPU overhead and if the particular device is equipped with
the DMA controller, the MibSPI may use the DMA controller to receive or
transmit data directly to or from memory.
6.1
Compatibility Mode
When use in compatibility mode, the MibSPI module uses one DMA request
enable bit (DMA REQ EN).
When a character is being transmitted or received, the MibSPI will signal the
DMA via a DMA request signal. The DMA controller will then perform the
needed data manipulation.
For DMA-based transmissions, all characters are assembled in RAM, and
DMA transfers move the message, word-by-word, from RAM into the
SPIDAT0 register. (See the DMA controller specification). Data is then read
from SPIBUF, clearing RXINTFLAG (SPICTRL3.0).
For efficient behavior, during DMA operations, the receive interrupt enable
flag RXINTEN (SPICTRL3.1) should be cleared to 0. For specific DMA
features, refer to the DMA controller specification.
6.2
Multi-buffer Mode
When multi-buffer mode is used, the DMA request bit in the SPICRTL 3
register is discarded. Only the DMA to buffers are allowed.
The MibSPI offers up to eight DMA channels (SEND/RECEIVE). All the DMA
channels are programmable individually and could be hooked to every buffer.
The DMA transfer could be trigger on Transmit, on receive or on both events.
Each DMA channel has the possibility to transfer a block of up to 32 data
without interruption using only one buffer of the array. This enables the
transfer of memory block from or into an external SPI memory. For example,
a group transfer could be set with three buffers of commands and a buffer
hooked to a DMA channel with a no break condition.
Summary of Contents for TMS470R1x
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