MibSPI Operation Modes
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
15
Figure 6.
Clock Mode with POLARITY = 0 and PHASE = 0
Figure 7.
Clock Mode with POLARITY = 0 and PHASE = 1
D6
2
Clock polarity = 0, Clock phase = 0
Write SPIDAT
SPICLK
SPISIMO
SPISOMI
Sample in
reception
MSB
D5
D4
D3
D2
D1
D0
LSB
D6
D5
D4
D3
D2
D1
D7
Clock phase = 0 (SPICLK without delay)
- Data is output on the rising edge of SPICLK
- Input data is latched on the falling edge of SPICLK
- A write to the SPIDAT register starts SPICLK
1
3
4
5
6
7
8
Clock polarity = 0, Clock phase = 1
Write SPIDAT
SPICLK
SPISIMO
SPISOMI
Sample in
reception
MSB
D6
D5
D4
D3
D2
D1
LSB
D6
D5
D4
D3
D2
D1
D7
1
2
3
4
5
6
7
8
D0
Clock phase = 1 (SPICLK with delay)
- Data is output one-half cycle before the first rising of SPICLK and on subsequent falling
edges of SPICLK
- Input data is latched on the rising edge of SPICLK
Summary of Contents for TMS470R1x
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