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MibSPI Operation Modes
20
TRIGEVT are not taken into account by the sequencer, so only the SPISCS
pins could trigger a Transfer Group. The chip-select trigger operates as a
level sensitive trigger. The PRST and ONESHOT field should be set to 0.
If the corresponding Transfer Group is enabled, the multi-buffer reads the
current buffer of the TG and writes it into SPIDAT1. If the Transfer Group is
disabled the multi-buffer does not update the SPIDAT1 register.
Note:
If the Transfer Group is disabled and no update of the SPIDAT1 register has
been done, the data to be transferred is meaningless.
Figure 12.
Multi-buffer in Slave Mode
When the SPIDAT1 register is updated, the enable signal is released, and the
transaction could begin. If the enable signal is not used, the master should
wait for six ICLK cycles before sending the clock to begin the transaction. This
time allows the MibSPI to update the SPIDAT1 register.
CTRL & Tx
STAT & Rx
Buffer RAM
SPIDAT1
SPIBUF
Shift register
Parity
SIMO
SOMI
CLK
ENA
Seq
TG 14
trigger
CS decoder
SPISCS[3:0]
TG 0
trigger
Summary of Contents for TMS470R1x
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