Control Registers and RAM
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
77
7.21
Transfer Group Interrupt Enable Register (TGINTENA)
The register TGINTENA comprises the transfer group interrupt enable flags
for “transfer finished” and for “transfer suspended”. The number of
implemented transfer groups is dependent on the MibSPI macro-cell. Each of
the enable bits in the higher half-word and the lower half-word of TGINTENA
belongs to one transfer group. In below register map a super-set MibSPI with
16 transfer groups is assumed. The real number of interrupt enable bits
depends on the implemented number of transfer groups.
Bits 31:16
INTENRDYx.
Transfer group interrupt enable when transfer finished
1 =
A interrupt is asserted when the transfer from transfer group x has
been finished.
0 =
No interrupt at the end of a transfer group transfer.
Bits 15:0
INTENSUSx.
Transfer group interrupt enable when transfer suspended
1 =
A interrupt is asserted when a transfer from transfer group x is sus-
pended.
0 =
No interrupt due to suspending of a transfer group transfer.
Bits
31
30
29
28
27
26
25
24
05Ch INTENRDY15 INTENRDY14 INTENRDY15 INTENRDY12 INTENRDY11 INTENRDY10 INTENRDY9 INTENRDY8
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Bits
23
22
21
20
19
18
17
16
INTENRDY7 INTENRDY6 INTENRDY5 INTENRDY4 INTENRDY3 INTENRDY2 INTENRDY1 INTENRDY0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Bits
15
14
13
12
11
10
9
8
INTENSUS15 INTENSUS14 INTENSUS13 INTENSUS12 INTENSUS11 INTENSUS10 INTENSUS9
INTENSUS8
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Bits
7
6
5
4
3
2
1
0
INTENSUS7
INTENSUS6
INTENSUS5
INTENSUS4
INTENSUS3
INTENSUS2
INTENSUS1
INTENSUS0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Legend: R = Read, W = Write, C = Clear, U = Undefined,
-n
= Value after reset, x = indeterminate
Summary of Contents for TMS470R1x
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