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Control Registers and RAM
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
43
Bit 4
SPIEN.
SPI enable
Holds the MibSPI in a reset state after a chip reset. The MibSPI is enabled
only after a 1 is written to this bit. This bit must be set to 1 after all other
MibSPI configuration bits have been written. This prevents an invalid
operation of the MibSPI while the clock polarity is being changed. When this
bit is 0, the MibSPI shift registers (SPIDAT0 and SPIDAT1) is held in reset
mode and forced to 0x0000.
The RXINTFLAG (SPICTRL3.0) and RCVROVRN (SPITRL3.2) bits are also
held in reset mode and forced to 0 when this bit is 0. SPICLK is disabled when
this bit is 0.
0 =
MibSPI is in reset
1 =
Activates MibSPI
Bit 3
MASTER.
SPISIMO/SPISOMI pin direction determination.
Determines the direction of the SPISIMO and SPISOMI pins.
0 =
SPISIMO pin an input, SPISOMI pin an output
1 =
SPISOMI pin an input, SPISIMO pin an output
Bit 2
POWERDOWN.
When active, the MibSPI state machines enter a powerdown state.
0 =
MibSPI in active mode
1 =
MibSPI in powerdown mode
Bit 1
POLARITY.
Controls the polarity of the SPICLK. Clock polarity and clock phase
(SPICTRL2.0) controls four clocking schemes on the SPICLK pin. See Figure
6 to Figure 9, page -15 for wave form diagrams of the MibSPI clocking
schemes.
Bit 0
PHASE.
Data is sent or latched in-phase with the clock signal. When PHASE = 1,
SPICLK is delayed by one-half cycle from when data is output. Polarity is
determined by the POLARITY bit (SPICTRL2.1). POLARITY and PHASE
make four different clocking schemes possible. For information on the use of
the Polarity and Phase bits, see section 2.5,
Note: Register Configuration Bits
Since there are configuration bits in this register, two write operations must
occur when setting these bits. One write to set the configuration bits and one
to set the SPIEN bit.
Summary of Contents for TMS470R1x
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