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MibSPI Operation Modes
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
5
2.1
MibSPI Internal Registers
A general representation of the MibSPI internal registers is shown in Table 1.
The page column provides a cross reference to additional information on the
individual registers. For more information regarding individual bytes, see
Table 3, on page 30.
Table 1.
MibSPI Internal Registers Mode
†‡
Offset
Address
†
Mnemonic
Name
Description
Page
0x00
SPICTRL1
SPI Control Register 1
Sets transfer rate and character length
0x04
SPICTRL2
SPI Control Register 2
Controls SPI clock
0x08
SPICTRL3
SPI Control Register 3
Controls system interface
0x0C
SPIDAT0
SPI Shift Register 0
Main shift register
0x10
SPIDAT1
SPI Shift Register 1
Shift register used in automatic slave chip
select mode only
0x14
SPIBUF
SPI Buffer Register
Holds received word
0x18
SPIEMU
SPI Emulation Register
Mirror of SPIBUF. Read does not clear
flags
0x1C
SPIPC1
SPI Pin Control Register 1
Controls the direction of data on the I/O
pins
0x20
SPIPC2
SPI Pin Control Register 2
Reflects the values on the I/O pins
0x24
SPIPC3
SPI Pin Control Register 3
Controls the values sent to the I/O pins
0x28
SPIPC4
SPI Pin Control Register 4
Sets data values in the SPIPC3 register
0x2C
SPIPC5
SPI Pin Control Register 5
Clears values in the SPIPC3 register
0x30
SPIPC6
SPI Pin Control Register 6
Determines if pins will operate as general
I/O or SPI functional pin.
040h
SPICTRL4
Control Register 4
Enables MibSPI mode
044h
SPICTRL5
Control Register 5
Sets CS mode, CS pre-/post-transfer
delay time and ENA time-out
†
The actual address of these registers is device specific and CPU specific. See the specific device data sheet to verify the
MibSPI register addresses.
‡
The shaded registers are only accessible in MibSPI mode, registers from 0x00 to 0x30 are compatible with the TMS470
SPI module (SPNU195)
Summary of Contents for TMS470R1x
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