Control Registers and RAM
80
Bits 15:0
INTFLGSUSx.
Transfer group interrupt flag for “transfer suspend” interrupt.
These flag are read/clear register.Reading the interrupt vector registers
TGINTVECT0 or TGINTVECT1 is clearing automatically the referenced
interrupt flag INTFLGSUSx.
1 =
A “transfer suspended” interrupt from transfer group x occurred. No
matter whether the interrupt is enabled or disabled (INTENSUSx =
don’t care) or whether the interrupt is mapped to line INT0 or INT1,
INTFLGSUSx is set right after the transfer from transfer group x is sus-
pended.
Writing a one (1) in bit field will clear the corresponding bit flag.
0 =
No ”transfer suspended” interrupt occurred since last clearing of the
flag INTFLGSUSx.
Writing a zero (0) has no effect.
Summary of Contents for TMS470R1x
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