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Control Registers and RAM
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
83
7.25
Transfer Group Interrupt Vector Register 1 (TGINTVECT1)
The register TGINTVECT1 returns a vector of the highest prior interrupt that
is enabled for interrupt line INT1, no matter whether it is a “transfer finished”
interrupt or a “transfer suspended” interrupt. The transfer group with the
lowest number (transfer group 0) has the highest priority.
Bits 31:6
Reserved
Bits 5:1
INTVECT1.
Interrupt vector for interrupt line INT1.
INTVECT1 returns the vector of the pending interrupt at interrupt line INT1. If
more than one interrupt is pending, INTVECT1 always references the highest
prior interrupt source first. The transfer group with the smallest number has
the highest priority. Reading INTVECT1 automatically updates the
TGINTVECT1 register with the interrupt vector coming next in the interrupt
priority chain and the corresponding type (SUSPEND flag). Error interrupts
have lowest priority.
Bits 0
SUSPEND.
“Transfer suspended” or “transfer finished” interrupt.
Every time TGINTVECT1 is read by the host the corresponding interrupt flag
of the referenced transfer group is cleared and TGINTVECT1 is updated with
the vector coming next in the priority chain. In parallel the SUSPEND flag is
updated depending on the type of interrupt.
1 =
The interrupt type is a “transfer suspended” interrupt. I.e. the transfer
group referenced by INTVECT1 has asserted an interrupt, because the
buffer to be transferred next is in “suspend to wait” mode.
0 =
The interrupt type is a “transfer finished” interrupt. I.e. the transfer
group referenced by INTVECT1 has asserted an interrupt, because all
data from the whole transfer group has been transferred.
Bits
31
16
06Ch
Reserved
U
Bits
15
6
5
0
Reserved
INTVECT1
SUSPEND
U
R-0
R-0
Legend: R = Read, W = Write, C = Clear, U = Undefined,
-n
= Value after reset, x = indeterminate
Summary of Contents for TMS470R1x
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