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Control Registers and RAM
40
Bits 12:5
PRESCALE.
Determines the bit transfer rate if the MibSPI is the network master. There are
255 data transfer rates (each a function of the interface clock) that can be
selected. One data bit is shifted per SPICLK cycle.
If the MibSPI is a network slave, the module receives a clock signal on the
SPICLK pin from the network master.
MibSPI Baud Rate for PRESCALE = 1 to 255
MibSPI Baud Rate for PRESCALE = 0
Bits 4:0
CHARLEN.
Controls how many times the MibSPI shifts per character transmitted or the
number of bits per character. The binary value of the bit length must be
programmed into this register. Legal values are 0x02 to 0x10. Illegal values,
such as 0x00 or 0x1F are not detected and their effect is indeterminate.
Note: CHARLEN Bits Must Be Initialized
CHARLEN.4:0 must be initialized to the desired character length before the
SPIEN bit is set. Otherwise, the first character may be shifted with an
incorrect length.
SPIBaudRate
ICLK
PRESCALE
1
+
(
)
-------------------------------------------------
=
SPIBaudRate
ICLK
2
--------------
=
Summary of Contents for TMS470R1x
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