MibSPI Operation Modes
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
7
Table 1.
MibSPI Internal Registers Mode
†‡
(Continued)
2.2
MibSPI Operation; Three-Pin Option
In master mode configuration (MASTER=1 (SPICTRL2.3) and CLKMOD=1
(SPICTRL2.5)), the MibSPI provides the serial clock on the SPICLK pin for
the entire serial communications network. Data is output on the SPISIMO pin
and latched in from the SPISOMI pin (see Figure 2).
Figure 2.
MibSPI Three-Pin Option
Data written to the shift register (SPIDAT0) initiates data transmission on the
SPISIMO pin, most significant bit (MSB) first. Simultaneously, received data
is shifted through the SPISOMI pin into the least significant bit (LSB) of the
Offset
Address
†
Mnemonic
Name
Description
Page
0D8h...
0FFh
Reserved
Reserved
base1 +
000h...
1FFh
CTRL+TX
buffers
Multi-buffer RAM Read/
Write Addresses
Transmit and control RAM
200h
3FFh
STAT+RX
buffers
Multi-buffer Read-only
Addresses
Receive and status RAM
†
The actual address of these registers is device specific and CPU specific. See the specific device data sheet to verify the
MibSPI register addresses.
‡
The shaded registers are only accessible in MibSPI mode, registers from 0x00 to 0x30 are compatible with the TMS470
SPI module (SPNU195)
MibSPI three pin option
Master
Slave
(Master = 1 ; CLKMOD = 1)
(Master = 0 ; CLKMOD = 0)
SPIDAT0
SPIDAT0
MSB
LSB
MSB
LSB
Write to
SPISOMI
SPISIMO
SPISOMI
SPISIMO
SPICLK
SPICLK
Write to SPIDAT
SPICLK
SIMO
SOMI
Summary of Contents for TMS470R1x
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