Control Registers and RAM
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
97
When one of the “skip” modes is selected, the sequencer checks the buffer
status every time it comes along. If the current buffer status (TXFULL,
RXEMPTY) does not match the buffer is skipped without data transfer.
When one of the “suspend” modes is selected, the sequencer checks the
buffer status and if it doesn’t match it waits until it matches. I.e. no data
transfer is initiated until the status condition of the concerned buffer matches.
Bit 12
CSHOLD.
Chip select hold mode
CSHOLD is considered in master mode only. In slave mode this bit has no
meaning. CSHOLD defines the behavior of the chip select line at the end of
a data transfer.
1 =
The chip select signal is held active at the end of a transfer until a con-
trol field with new chip select information is loaded into the MibSPI ker-
nel. If the new chip select information equals the previous one the
active chip select signals is extended until end of a transfer with
CSHOLD cleared or until the chip select information changes.
If CSHOLD is set in the control field of the last buffer to be transferred,
then the corresponding chip select signal stays active until a new trans-
fer is initiated.
0 =
The chip select signal is deactivated at the end of a transfer after the
T2CDELAY time has passed. If two transfers are dedicated to the
same chip select the appropriate chip select signal will be shortly deac-
tivated before it is activated again.
Bit 11
LOCK.
Lock two consecutive buffers to be transmit without being interrupted
by a transfer group that has higher priority.
1 = The transfer of this buffer and the buffer located at the next address is
not interruptible.
0 = Any higher interruption could occurs after the end of the current transac-
tion.
Bit 10
WDEL.
Enable the delay counter at the end of the current transaction.
1 = after the transaction WDELAY of the corresponding data format is loaded
into the delay counter. No transaction is performed until the counter is
reset.
0 = No delay is inserted.
Summary of Contents for TMS470R1x
Page 2: ...2 ...