![background image](http://html.mh-extra.com/html/texas-instruments/tms470r1x/tms470r1x_reference-manual_1097091093.webp)
Control Registers and RAM
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
85
7.26
Tick Count Register (TICKCNT)
One of the trigger sources for transfer groups is a MibSPI internal periodic
time trigger. This time trigger is called tick counter and is basically a down-
counter with a pre-load/reload value. Every time the tick counter detects an
under-flow it reloads the initial value and toggles the trigger signal provided
to the transfer groups.
The above shown trigger signal as a square wave signal support very well the
different trigger event types for the transfer groups (e.g. falling edge, rising
edge and both edges).
Bit 31
TICKENA.
Tick counter enable.
1 =
The MibSPI internal tick counter is enabled and is clocked by the clock
source selected by CLKCTRL[1:0]. When the tick counter is enabled it
starts down-counting from its current value. When TICKENA goes from
“0” to “1” the tick counter is automatically loaded with the TICKVALUE.
0 =
The MibSPI internal tick counter is disabled. The counter value
remains unchanged.
Note:
When the tick counter is disabled the trigger signal is forced low.
Bits
31
30
29
28
27
16
070h TICKENA RELOAD
CLKCTRL
Reserved
RW-0
R0S-0
RW-0
U
Bits
15
0
TICKVALUE
RW-0
Legend: R = Read, R0 = always read 0, W = Write, S = Set, C = Clear, U = Undefined,
-n
= Value after reset, x = indeterminate
Tick counter
Trigger signal
Counter reload
Summary of Contents for TMS470R1x
Page 2: ...2 ...