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Control Registers and RAM
54
7.10
MibSPI Pin Control Register 1 (SPIPC1)
Bits 31:12
Reserved.
Reads are undefined and writes have no effect
Bit 11:4
SCSDIR x.
SPISCSx direction.
Controls the direction of the SPISCSx pins when they are used as a general-
purpose I/O pin. Each pins could be configured independently from the others
If the SPISCSx is used as a SPI functional pin, the I/O direction is determined
by the CLKMOD bit (SPICTRL2.5).
0 =
SPISCSx pin is an input
1 =
SPISCSx pin is an output
Bit 3
SOMIDIR.
SPISOMI direction.
Controls the direction of the SPISOMI pin when it is used as a general-
purpose I/O pin. If the SPISOMI pin is used as a MibSPI functional pin, the I/
O direction is determined by the MASTER bit (SPICTRL2.3).
0 =
SPISOMI pin is an input
1 =
SPISOMI pin is an output
Bits
31
16
0x1C
Reserved
U
Bits
15
12
11
10
9
8
Reserved
SCSDIR7
SCSDIR6
SCSDIR5
SCSDIR4
U
RW-0
RW-0
RW-0
RW-0
Bits
7
6
5
4
3
2
1
0
SCSDIR3
SCSDIR2
SCSDIR1
SCSDIR0
SOMIDIR
SIMOIDIR
CLKDIR
ENADIR
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Legend: R = Read, C = Clear, U = Undefined;
-n =
Value after reset
Summary of Contents for TMS470R1x
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