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Control Registers and RAM
70
7.18
SPI Control Register 6 (SPICTRL6)
Bits 31:8
Reserved
Bits 7:0
CSDEFx.
Chip select default pattern.
Master mode behavior.
The CSDEFx register is output to the chip select pin when no transmission
are currently performed. It allows the user to set a chip select pattern which
deselect all the SPI slaves.
1 =
If CSDEFx is set to “1” the corresponding chip select is set to “1” when
no transfer occurs.
0 =
If CSPOLx is set to “0” the corresponding chip select is set to “0” when
no transfer occurs.
Bits
31
16
048h
Reserved
U
Bits
15
8
Reserved
U
Bits
7
6
5
4
3
2
1
0
CSDEF7
CSDEF6
CSDEF5
CSDEF4
CSDEF3
CSDEF2
CSDEF1
CSDEF0
RW-1
RW-1
RW-1
RW-1
RW-1
RW-1
RW-1
RW-1
Legend: RW = Read/Write, U = Undefined,
-n
= Value after reset, x = indeterminate
Summary of Contents for TMS470R1x
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