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Texas Instruments TMS470R1x, Reference Manual

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Texas Instruments TMS470R1x Reference Manual Download Page 36

Interrupts

28

Figure  13.

Transfer Group Interrupt Structure

During transmission, if one of the following error occurs: BITERR, DESYNC,
PARITYERR, TIMEOUT. The corresponding flag in the SPISTAT register is
set. If the enable bit is set then an interrupt is generated. The level of the
interrupt could be generated according to the bit field in SPISTAT. 

The error interrupt are enabled, and prioritized independently from each
other, but the vector generated by the MibSPI will be the same if multiple error
are enabled on the same level.

Figure  14.

SPISTAT Interrupt Structure

LVL 0

LVL 1

LVLx

ENAx

Finished

Suspended

Transfer

group x

Bit 0

X + 1

Vector

LVLx

ENAx

LVL 1

LVL 0

PARITYERR

DESYNC

BITERR

TIMEOUT

Summary of Contents for TMS470R1x

Page 1: ...TMS470R1x Multi Buffer Serial Peripheral Interface MibSPI Reference Guide Literature Number SPNU217B October 2003 ...

Page 2: ...2 ...

Page 3: ...REVISION HISTORY REVISION DATE NOTES B 10 03 Register formats updated Pages 30 101 A 9 02 Converted to stand alone book 9 02 Initial version ...

Page 4: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

Page 5: ...alization 19 2 9 Multiple Chip Select Master only 19 2 10 Slave Mode in Multi buffer Configuration 19 2 11 Internal Loop Back Test Mode Master only 21 2 12 Transmission Continuous Self test Master only 21 2 13 Variable Chip Select Setup and Hold Timing Master only 21 2 14 Lock Transmission 23 2 15 Hold Chip Select Active Master only 23 2 16 Detection of Slave De synchronization Master only 23 2 17...

Page 6: ...PICTRL4 65 7 17 SPI Control Register 5 SPICTRL5 66 7 18 SPI Control Register 6 SPICTRL6 70 7 19 SPI Control Register 7 SPICTRL7 SPICTRL8 SPICTRL9 71 7 20 SPI Status Register SPISTAT 74 7 21 Transfer Group Interrupt Enable Register TGINTENA 77 7 22 Transfer Group Interrupt Level Register TGINTLVL 78 7 23 Transfer Group Interrupt Flag Register TGINTFLAG 79 7 24 Transfer Group Interrupt Vector Regist...

Page 7: ...OLARITY 1 and PHASE 0 16 9 Clock Mode with POLARITY 1 and PHASE 1 16 10 Five Bits per Character Five Pin Option 17 11 Example Different Modes for a Multi buffer RAM of 64 Buffers 18 12 Multi buffer in Slave Mode 20 13 Transfer Group Interrupt Structure 28 14 SPISTAT Interrupt Structure 28 15 Example tC2TDELAY 8 ICLK cycles 66 16 Example tT2CDELAY 4 ICLK cycles 67 17 Transmit data finished to ENA i...

Page 8: ...de 5 2 Clocking Modes 14 3 MibSPI Registers 30 4 MibSPI RAM 37 5 Interrupt Vector for Interrupt Line INT0 82 6 Interrupt Vector for Interrupt Line INT1 84 7 Trigger Event Types 90 8 Trigger Sources 91 9 Buffer Mode Selection Bits BUFMODE 2 0 96 ...

Page 9: ...SPI is in effect a programmable length shift register used for high speed communication between external peripherals or other microcontrollers Its multi buffer allows multiple transmissions with different peripherals without any CPU action 1 Overview 2 2 MibSPI Operation Modes 3 3 General Purpose I O 25 4 Low Power Mode 26 5 Interrupts 27 6 DMA Interface 29 7 Control Registers and RAM 30 Topic Pag...

Page 10: ...ers I O etc or by the internal tick counter The internal tick counter can support periodic trigger events Each buffer can be associated with different DMA channels in different transfer groups allowing the user to move data from to internal memory to from external slave with a minimal CPU interaction The pins SPICLK SPISIMO and SPISOMI are used in all MibSPI pin modes The pins SPIENA and SPISCS 7 ...

Page 11: ...ting with multiple slave devices When the master MibSPI sending out the clock stream writes to SPIDAT1 the SPISCS pins are automatically driven to select the slave connected to that signal Writing to SPIDAT0 will not drive any SPISCS pins thus allowing the master to communicate with all slave devices connected to the same SPI bus In addition a handshaking mechanism provided by the SPIENA pin enabl...

Page 12: ...AM access control unit Ctrl regs Event mgmt Tick count Buffer array mgmt Sequencer 13 2 16 Buffer Ctrl stat info Ctrl regs Parity Shift register DMAreq Int0 Int1 SIMO SOMI CLK ENA SCS0 SCSx DMAreq MIBspi DMA controller External event Expansion bus MibSPI interface including multi buffer RAM and sequencer MibSPI kernel ...

Page 13: ...d word 49 0x18 SPIEMU SPI Emulation Register Mirror of SPIBUF Read does not clear flags 53 0x1C SPIPC1 SPI Pin Control Register 1 Controls the direction of data on the I O pins 54 0x20 SPIPC2 SPI Pin Control Register 2 Reflects the values on the I O pins 56 0x24 SPIPC3 SPI Pin Control Register 3 Controls the values sent to the I O pins 57 0x28 SPIPC4 SPI Pin Control Register 4 Sets data values in ...

Page 14: ...sfer suspended event 79 068h TGINTVE CT0 TG Interrupt Vector Transfer group interrupt vector for line INT0 81 06Ch TGINTVE CT1 TG Interrupt Vector Transfer group interrupt vector for line INT1 83 070h TICKICNT Initial Tick Count Value Initial tick count value defines periodic trig ger to start group transfers 85 074h LTGPEND MibSPI Last Transfer Group End Address Defines the end address for the la...

Page 15: ...is shifted through the SPISOMI pin into the least significant bit LSB of the Offset Address Mnemonic Name Description Page 0D8h 0FFh Reserved Reserved base1 000h 1FFh CTRL TX buffers Multi buffer RAM Read Write Addresses Transmit and control RAM 96 200h 3FFh STAT RX buffers Multi buffer Read only Addresses Receive and status RAM 99 The actual address of these registers is device specific and CPU s...

Page 16: ...k master to send the SPICLK signal and then shifts data on the SPISIMO pin into the SPIDAT0 register If data is to be transmitted by the slave simultaneously it must be written to the SPIDAT0 register before the beginning of the SPICLK signal When the MIPSPI mode is enabled the three pin option works by setting all the SPISCS pins in GPIO mode The chip select field in the buffers becomes meaningle...

Page 17: ...re going to be used must be configured as functional SPIPC6 11 4 The default pattern to be put on the SPISCS 7 0 when all the slave are deactivate is set in the SPICRTL6 register This pattern allows a different slave with different chip select polarity to be activated by the MibSPI During transmission the CSNR field of the SPIDAT1 register or of the current buffer is applied on the pins this patte...

Page 18: ...in Option Hardware Handshaking To use the hardware handshaking mechanism both the SPIENA pin and SPISCS 7 0 pin must be configured as functional pins Compatibility mode In the master SPI CLKMOD 1 the SPIENA pin is configured as a functional input If configured as a slave SPI the SPIENA pin is configured as a functional output If the SPIENA pin is in high z mode ENABLE_HIGHZ 1 the slave SPI will pu...

Page 19: ...llowing the master SPI to communicate with other slave SPIs Figure 5 MibSPI Five Pin Option with SPIENA and SPISCS In the master SPI CLKMOD 1 the SPISCS pin is configured as a functional output If configured as a slave SPI CLKMOD 0 the SPISCS pin is configured as a functional input A write to the master s SPIDAT1 shift register will automatically drive the SPISCS signal low The master will drive t...

Page 20: ... how a 14 bit word is stored in the buffer once it is received In transmit mode the SPIBUF register contains the most recently transmit ted word left justified The diagram below shows how a 14 bit word needs to be written to the buffer in order to be transmitted correctly To allow for the efficient transmission of byte sized words if a character length is programmed for 8 bits or less the SDPDAT 7...

Page 21: ...st If it is written right aligned into the MibSPI the internal shift register will sort out the correct transfer according to selected shift direction and data word length To increase fault detection of data transmission and reception an odd or even parity bit can be enabled to be transmitted at the end of a data word The parity generator can be enabled or disabled individually for each buffer If ...

Page 22: ...nals of SPICLK corresponding to each mode Having four signal options allows the MibSPI to interface with different types of serial devices Also shown are the SPICLK control bit polarity and phase values corresponding to each signal POLARITY PHASE ACTION 0 0 Data is output on the rising edge of SPICLK Input data is latched on the falling edge 0 1 Data is output one half cycle before the first risin...

Page 23: ...phase 0 SPICLK without delay Data is output on the rising edge of SPICLK Input data is latched on the falling edge of SPICLK A write to the SPIDAT register starts SPICLK 1 3 4 5 6 7 8 Clock polarity 0 Clock phase 1 Write SPIDAT SPICLK SPISIMO SPISOMI Sample in reception MSB D6 D5 D4 D3 D2 D1 LSB D6 D5 D4 D3 D2 D1 D7 1 2 3 4 5 6 7 8 D0 Clock phase 1 SPICLK with delay Data is output one half cycle b...

Page 24: ...out delay Data is output on the falling edge of SPICLK A write to the SPIDAT register starts SPICLK Input data is latched on the rising edge of SPICLK Clock polarity 1 Clock phase 1 Write SPIDAT SPICLK SPISIMO SPISOMI Sample in reception MSB D6 D5 D4 D3 D2 D1 D0 LSB D6 D5 D4 D3 D2 D1 D7 Clock phase 1 SPICLK with delay Data is output one half cycle before the first falling edge of SPICLK and on the...

Page 25: ... two devices using a character length of five bits Figure 10 Five Bits per Character Five Pin Option 7 6 5 4 3 7 6 3 4 5 7 6 5 4 3 7 6 3 4 5 Master SPI Int flag Slave SPI Int flag SPISOMI from slave SPISIMO from master Clock polarity 1 Clock phase 1 SPISCS SPICLK signal options K B SPIENA Clock polarity 1 Clock phase 0 Clock polarity 0 Clock phase 1 Clock polarity 0 Clock phase 0 ...

Page 26: ...l bit Up to 15 trigger sources are available which can be utilized by each transfer group One of these trigger sources is called tick counter This tick counter is implemented in the MibSPI and generates periodic trigger events Other trigger sources can be MibSPI external signals coming from another peripheral module like the High End Timer HET or a general purpose input pin GPIO An interrupt can b...

Page 27: ...chip select control field CSNR 7 0 of the SPIDAT1 register SPIDAT1 23 16 is applied to the pins When the transmission finishes the default register value CSDEF is applied to the chip select pins To connect the MibSPI with encoded slave devices the CSNR field allows multiple active bits at a time The user could apply any value from 0 to 255 to provide a binary encoded chip select signal via the eig...

Page 28: ...s not update the SPIDAT1 register Note If the Transfer Group is disabled and no update of the SPIDAT1 register has been done the data to be transferred is meaningless Figure 12 Multi buffer in Slave Mode When the SPIDAT1 register is updated the enable signal is released and the transaction could begin If the enable signal is not used the master should wait for six ICLK cycles before sending the cl...

Page 29: ...PI transmit path and receive path including the buffers and the parity generator In this mode the transmit signal is internally fed back to the receiver whereas the SIMO SOMI and CLK pin are disconnected The transmitted data is internally transferred to the corresponding receive buffer while external signals remain unchanged This mode allows the CPU to write into the transmit buffer and check that...

Page 30: ...data transmission after the chip select is activated A second 5 bit delay counter can be configured to delay the chip select deactivation after the last data bit transfer Both delay counters are clocked with ICLK see section 7 17 Note If the CSHOLD bit is set within the control field the current hold time and the following set up time will not be applied in between transactions ...

Page 31: ...hip select set up time delay applied at the beginning of the following transaction However the wait delay could be still applied between the two transactions if the bit WDEL is set within the control field Note When CSHOLD is active no transmission interruptions are allowed The LOCK bit does not keep the CS active 2 16 Detection of Slave De synchronization Master only When a slave supports generat...

Page 32: ...ing the MibSPI by a non responsive slave device a time out value can be configured If the time out counter expires before an active ENA signal is sampled the TIMEOUT flag in the status register SPISTAT is set and the TIMEOUT flag in the status field of the corresponding buffer is set Note When the CS becomes active no transmission interruption are allowed The next arbitration is done while waiting...

Page 33: ... I O pin When the MibSPI module is not used the MibSPI pins may be programmed to be either general input or general output pins The direction is controlled in the SPIPC1 register Note that each pin can be programmed to be either a SPI pin or a GPIO pin through register SPIPC6 If the MibSPI function is used application software must ensure that each pin is configured as a MibSPI pin and not a GPIO ...

Page 34: ... written to or read from any register A local low power mode has the same effect when both the local POWERDOWN bit and the system level PPWNOVR bit are set If only the local POWERDOWN bit is set then the MibSPI logic is not clocked but the registers continue to be clocked Since entering a low power mode has the effect of suspending all state machine activities care must be taken when entering such...

Page 35: ...r mode the MibSPI could generates vectorized interrupt on two levels The overrun interrupt and receive interrupt are disabled and therefore the enable bits within the SPICTRL3 are discarded The interrupts available are Transfer group completed Transfer group suspended Transmission error When a transfer group has finished and the corresponding enable bit in the TGINTENA register is set an interrupt...

Page 36: ... is generated The level of the interrupt could be generated according to the bit field in SPISTAT The error interrupt are enabled and prioritized independently from each other but the vector generated by the MibSPI will be the same if multiple error are enabled on the same level Figure 14 SPISTAT Interrupt Structure LVL 0 LVL 1 LVLx ENAx Finished Suspended Transfer group x Bit 0 X 1 Vector LVLx EN...

Page 37: ...the DMA controller specification Data is then read from SPIBUF clearing RXINTFLAG SPICTRL3 0 For efficient behavior during DMA operations the receive interrupt enable flag RXINTEN SPICTRL3 1 should be cleared to 0 For specific DMA features refer to the DMA controller specification 6 2 Multi buffer Mode When multi buffer mode is used the DMA request bit in the SPICRTL 3 register is discarded Only t...

Page 38: ... Register 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0x00 SPICTRL1 Reserved WAIT ENAx PARI TYx Reserv ed PRESCALE 7 0 CHARLEN 4 0 0x04 SPICTRL2 Reserved LOOP BACK Reserved WDELAYx SHIFT DIR PAR POL CLK MOD SPI EN MASTER POWER DOWN POLAR ITY PHASE 0x08 SPICRTL3 Reserved Reserved ENABLE HIGHZ DMA REQ EN OVRN INTEN RCVR OVRN RXINT EN RXINT FLAG 0x0C SPIDAT0 ...

Page 39: ...S DIR 3 SCS DIR 2 SCS DIR 1 SCS DIR 0 SOMI DIR SIMO DIR CLK DIR ENABLE DIR 0x20 SPIPC2 Reserved Reserved SCS DIN 7 SCS DIN 6 SCS DIN 5 SCS DIN 4 SCS DIN 3 SCS DIN 2 SCS DIN 1 SCS DIN 0 SOMI DIN SIMO DIN CLK DIN ENABLE DIN 0x24 SPIPC3 Reserved Reserved SCS DOUT 7 SCS DOUT 6 SCS DOUT 5 SCS DOUT 4 SCS DOUT 3 SCS DOUT 2 SCS DOUT 1 SCS DOUT 0 SOMI DOUT SIMO DOUT CLK DOUT ENABLE DOUT 0x28 SPIPC4 Reserve...

Page 40: ...OUT CLR 4 SCS DOUT CLR 3 SCS DOUT CLR 2 SCS DOUT CLR 1 SCS DOUT CLR 0 SOMI DOUT CLR SIMO DOUT CLR CLK DOUT CLR ENABLE DOUT CLR 0x30 SPIPC6 Reserved Reserved SCS FUN 7 SCS FUN 6 SCS FUN 5 SCS FUN 4 SCS FUN 3 SCS FUN 2 SCS FUN 1 SCS FUN 0 SOMI FUN SIMO FUN CLK FUN ENABLE FUN 0x34 Reserved Reserved 0x38 Reserved Reserved 0x3C Reserved Reserved 0x40 SPICTRL4 Reserved Reserved MIBSPI ENA Table 3 MibSPI...

Page 41: ... Reserved WDELAYx SHIFT DIRx PAR POL Reserved POLARI TYx PHASEx WAIT ENAx PARI TYx Reserv ed PRESCALEx CHARLENx 0x50 SPICTRL 8 Reserved WDELAYx SHIFT DIRx PAR POL Reserved POLARI TYx PHASEx WAIT ENAx PARI TYx Reserv ed PRESCALEx CHARLENx 0x54 SPICTRL 9 Reserved WDELAYx SHIFT DIRx PAR POL Reserved POLARI TYx PHASEx WAIT ENAx PARI TYx Reserv ed PRESCALEx CHARLENx 0x58 SPISTAT Reserved BIT ERR LVL DE...

Page 42: ...DY5 INTLVL RDY4 INTLVL RDY3 INTLVL RDY2 INTLVL RDY1 INTLVL RDY0 INTLVL SUS15 INTLVL SUS14 INTLVL SUS13 INTLVL SUS12 INTLVL SUS11 INTLVL SUS10 INTLVL SUS9 INTLVL SUS8 INTLVL SUS7 INTLVL SUS6 INTLVL SUS5 INTLVL SUS4 INTLVL SUS3 INTLVL SUS2 INTLVL SUS1 INTLVL SUS0 0x64 TGINTFLG INTFLG RDY15 INTFLG RDY14 INTFLG RDY13 INTFLG RDY12 INTFLG RDY11 INTFLG RDY10 INTFLG RDY9 INTFLG RDY8 INTFLG RDY7 INTFLG RDY...

Page 43: ...ONE SHOT PRST TGTD Reserved TRGEVT TRIGSRC Reserv ed PSTART Reserv ed PCURRENT 0x7C TG1CTRL TG ENA ONE SHOT PRST TGTD Reserved TRGEVT TRIGSRC Reserv ed PSTART Reserv ed PCURRENT 0xB0 TG14CTRL TG ENA ONE SHOT PRST TGTD Reserved TRGEVT TRIGSRC Reserv ed PSTART Reserv ed PCURRENT 0xB4 TG15CTRL TG ENA ONE SHOT PRST TGTD Reserved TRGEVT TRIGSRC Reserv ed PSTART Reserv ed PCURRENT RX DMA ENA TX DMA ENA ...

Page 44: ...rs Offset Address Register 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0xB8 DMA0CTRL ONE SHOT BUFID RXDMACH TXDMACH 0xBC DMA1CTRL ONE SHOT BUFID RXDMACH TXDMACH RX DMA ENA TX DMA ENA NO BRK ICOUNT Reserved COUNT 0xD0 DMA6CTRL ONE SHOT BUFID RXDMACH TXDMACH RX DMA ENA TX DMA ENA NO BRK ICOUNT Reserved COUNT 0xD4 DMA7CTRL ONE SHOT BUFID RXDMACH TXDMACH RX DM...

Page 45: ...with the Chip select used by the MibSPI RAM the number of wait state WS should be set to WS 2 ICLK ratio Example For ICLK 3 SYSCLK then WS 2 3 5 Table 4 MibSPI RAM Offset Address Register 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0x00 Buffer 0 BUFMODE CS HOLD LOCK WDEL DFSEL CSNR TXDATA 0x04 Buffer 1 BUFMODE CS HOLD LOCK WDEL DFSEL CSNR TXDATA 0x1F8 Buff...

Page 46: ... ERR DE SYNC PARIT YERR TIME OUT Reserve d LCSNR RXDATA 0x204 Buffer 1 RXEMP TY RX OVR TX FULL BIT ERR DE SYNC PARIT YERR TIME OUT Reserve d LCSNR RXDATA 0x3F8 Buffer 126 RXEMP TY RX OVR TX FULL BIT ERR DE SYNC PARIT YERR TIME OUT Reserve d LCSNR RXDATA 0x3FC Buffer 127 RXEMP TY RX OVR TX FULL BIT ERR DE SYNC PARIT YERR TIME OUT Reserve d LCSNR RXDATA Table 4 MibSPI RAM Continued ...

Page 47: ...e out counter CE2DELAY expires 0 The MibSPI does not wait for the ENA signal from the slaves and directly starts the transfer Note This bit is only accessible in MibSPI mode Bit 14 PARITY0 Parity enable for data format 0 1 A parity is added after transfer of the data bit At the end of a transfer the parity generator compares the received parity bit with the locally calcu lated parity flag If the p...

Page 48: ...to 255 MibSPI Baud Rate for PRESCALE 0 Bits 4 0 CHARLEN Controls how many times the MibSPI shifts per character transmitted or the number of bits per character The binary value of the bit length must be programmed into this register Legal values are 0x02 to 0x10 Illegal values such as 0x00 or 0x1F are not detected and their effect is indeterminate Note CHARLEN Bits Must Be Initialized CHARLEN 4 0 ...

Page 49: ...ts an inactive value and SPISOMI remains in high impedance state The MibSPI has to be initialized in master mode before the loop back can be selected If the MibSPI is initialized in slave mode or a data transfer is ongoing errors may result 1 Internal loop back test mode enabled 0 Internal loop back test mode disabled Note This bit is only accessible in MibSPI mode Bits 15 14 Reserved Reads are un...

Page 50: ... Data format 0 shift direction Most significant bit is shifted out first Note This bit is only accessible in MibSPI mode Bit 6 PARPOL0 Parity polarity even or odd PARPOL0 can be modified in privilege mode only It can be used for data format 0 1 If PARPOL0 is set to 1 and SPICTRL 1 14 is enabled a odd parity flag is added at the end of the transmit data stream 0 If PARPOL0 is set to 0 and SPICTRL 1...

Page 51: ...s 0 SPISIMO pin an input SPISOMI pin an output 1 SPISOMI pin an input SPISIMO pin an output Bit 2 POWERDOWN When active the MibSPI state machines enter a powerdown state 0 MibSPI in active mode 1 MibSPI in powerdown mode Bit 1 POLARITY Controls the polarity of the SPICLK Clock polarity and clock phase SPICTRL2 0 controls four clocking schemes on the SPICLK pin See Figure 6 to Figure 9 page 15 for ...

Page 52: ...ot driving a low signal If inactive then the pin will output both a high and a low signal 0 SPIENA pin is a value 1 SPIENA pin is in high z Bit 4 DMA REQ EN DMA request enable Enables the DMA request signal to be generated for both receive and transmit channels 0 DMA is not used 1 DMA is used Bits 31 16 0x08 Reserved U Bits 15 8 Reserved U Bits 7 6 5 4 3 2 1 0 Reserved ENABLE HIGHZ DMAREQEN OVRNIN...

Page 53: ...RL3 3 is set high This bit is cleared in one of four ways Reading the SPIBUF register Writing a 1 to this bit Writing a 0 to SPIEN SPICTRL2 4 System reset 0 Overrun condition did not occur 1 Overrun condition has occurred Bit 1 RXINTEN An interrupt is to be generated when the RXINTFLAG bit SPICTRL3 0 is set by hardware Otherwise no interrupt will be generated 0 Interrupt will not be generated 1 In...

Page 54: ...be read after the shift operation is complete to determine what data was shifted into the SPIDAT0 register When transmitting data input data is automatically clocked in at the receive side As the data is shifted from the MSB the LSB of the received data is shifted in Similarly when the shift register is used as a receiver the shift register continues to send data out as it receives new data on eac...

Page 55: ...ip select information equals the previous one the active chip select signal is extended until the end of transfer with CSHOLD cleared or until the chip select information changes 0 The chip select signal is deactivated at the end of a transfer after the T2CDELAY time has passed If two consecutive transfers are dedi cated to the same chip select this chip select signal will be shortly deactivated b...

Page 56: ...ite to this register ONLY when using the automatic Slave Chip Select feature See section 2 MibSPI Operation Modes on page 3 A write to this register will drive the SPISCS signal low When data is read from this register the value is indeterminate because of the shift operation The value in the buffer register SPIBUF should be read after the shift operation is complete to determine what data was shi...

Page 57: ...ield Bit 30 RXOVR Receive data buffer overrun This flag is read clear only flag i e reading the flag will automatically clear it It has the same meaning as the RCVROVRNIMG flag at bit position 17 but is re mapped to bit 30 due to compatibility reason with the buffer status fields When a data transfer has been finished and the received data is copied into the SPIBUF while RXEMPTY flag is already cl...

Page 58: ...ad clear only flag i e reading the flag will automatically clear it De synchronization monitor is active in master mode only DESYNC represents a copy of the DESYNC flag in SPISTAT 1 A slave device is de synchronized The master monitors the ENA sig nal coming from the slave device and sets the DESYNC flag if ENA is deactivated before the last reception point or after the last bit is trans mitted pl...

Page 59: ... in the SPISTAT regis ter is set 0 No ENA signal time out occurred Bits 24 18 Reserved Reads are undefined and writes have no effect Bit 17 RCVR OVRN IMG MibSPI receiver overrun flag image This is a mirror bit of the RCVROVRN flag bit SPICTRL3 2 and is used to reduce the interrupt latency and execution time This bit is cleared in one of four ways Reading the SPIBUF register Writing a 1 to this bit...

Page 60: ... register SPIDAT Since the data is shifted into the MibSPI most significant bit first for word lengths less than 16 the data is stored right justified in the register Note MibSPI Buffer Reading the SPIBUF register clears the RCVROVRN SPICTRL3 2 RXINTFLAG SPICTRL3 0 RCVR OVRN IMG SPIBUF 17 and the RXINTFLAG IMG SPIBUF 16 bits ...

Page 61: ...ndefined and writes have no effect Bits 15 0 SPIEMU MibSPI emulation MibSPI emulation is a mirror of the SPIBUF register The only difference between SPIEMU and SPIBUF is that a read from SPIEMU does not clear the RCVR OVRN SPICTRL3 2 or RXINTFLAG SPICTRL3 0 bits Bits 31 16 0x18 Reserved U Bits 15 0 SPIEMU R U Legend R Read U Undefined n Value after reset ...

Page 62: ... 5 0 SPISCSx pin is an input 1 SPISCSx pin is an output Bit 3 SOMIDIR SPISOMI direction Controls the direction of the SPISOMI pin when it is used as a general purpose I O pin If the SPISOMI pin is used as a MibSPI functional pin the I O direction is determined by the MASTER bit SPICTRL2 3 0 SPISOMI pin is an input 1 SPISOMI pin is an output Bits 31 16 0x1C Reserved U Bits 15 12 11 10 9 8 Reserved ...

Page 63: ...1 SPISIMO pin is an output Bit 1 CLKDIR SPICLK direction Controls the direction of the SPICLK pin when it is used as a general purpose I O pin In functional mode the I O direction is determined by the CLKMOD bit SPICTRL2 5 0 SPICLK pin is an input 1 SPICLK pin is an output Bit 0 ENADIR SPIENA direction Controls the direction of the SPIENA pin when it is used as a general purpose I O If the SPIENA ...

Page 64: ...s the value of the SPISIMO pin 0 Current value on SPISIMO pin is logic 0 1 Current value on SPISIMO pin is logic 1 Bit 1 CLKDIN Clock data in Reflects the value of the SPICLK pin 0 Current value on SPICLK pin is logic 0 1 Current value on SPICLK pin is logic 1 Bit 0 ENADIN SPIENA data in Reflects the value of the SPIENA pin 0 Current value on SPIENA pin is logic 0 1 Current value on SPIENA pin is ...

Page 65: ...neral purpose I O pin and configured as an output pin The value of this bit indicates the value sent to the pin 0 Current value on SPISOMI pin is logic 0 1 Current value on SPISOMI pin is logic 1 Bit 2 SIMODOUT SPISIMO dataout write Only active when the SPISIMO pin is configured as a general purpose I O pin and configured as an output pin The value of this bit indicates the value sent to the pin 0...

Page 66: ...dicates the value sent to the pin 0 Current value on SPICLK pin is logic 0 1 Current value on SPICLK pin is logic 1 Bit 0 ENADOUT SPIENA dataout write Only active when the SPIENA pin is configured as a general purpose I O pin and configured as an output pin The value of this bit indicates the value sent to the pin 0 Current value on SPIENA pin is logic 0 1 Current value on SPIENA pin is logic 1 ...

Page 67: ... logic 0 1 Current value on SPISCSx pin is logic 1 Bit 3 SOMIDSET SPISOMI dataout set Only active when the SPISOMI pin is configured as a general purpose output pin A value of one written to this bit sets the corresponding SPISOMIDOUT bit SPIPC3 3 to one Write 0 Has no effect 1 Logic 1 placed on SPISOMI pin Read 0 Current value on SPISOMI pin is logic 0 1 Current value on SPISOMI pin is logic 1 Bi...

Page 68: ...se output pin A value of one written to this bit sets the corresponding CLKDOUT bit SPIPC3 1 to one Write 0 Has no effect 1 Logic 1 placed on SPICLK pin Read 0 Current value on SPICLK pin is logic 0 1 Current value on SPICLK pin is logic 1 Bit 0 ENADSET SPIENA dataout set Only active when the SPIENA pin is configured as a general purpose output pin A value of one written to this bit sets the corre...

Page 69: ...ogic 0 1 Current value on SPISCSx pin is logic 1 Bit 3 SOMIDCLR SPISOMI dataout clear Only active when the SPISOMI pin is configured as a general purpose output pin A value of one written to this bit clears the corresponding SPISOMIDOUT bit SPIPC3 3 to zero Write 0 Has no effect 1 Logic 0 placed on SPISOMI pin Read 0 Current value on SPISOMI pin is logic 0 1 Current value on SPISOMI pin is logic 1...

Page 70: ...e output pin A value of one written to this bit clears the corresponding CLKDOUT bit SPIPC3 1 to zero Write 0 Has no effect 1 Logic 0 placed on SPICLK pin Read 0 Current value on SPICLK pin is logic 0 1 Current value on SPICLK pin is logic 1 Bit 0 ENADCLR SPIENA dataout clear Only active when the SPIENA pin is configured as a general purpose output pin A value of one written to this bit clears the...

Page 71: ... functional pin Bit 3 SOMIFUN Slave out master in function Determines whether the SPISOMI pin is to be used as a general purpose I O pin or as a MibSPI functional pin 0 SPISOMI pin is a GPIO 1 SPISOMI pin is a MibSPI functional pin Bit 2 SIMOFUN Slave in master out function Determines whether the SPISIMO pin is to be used as a general purpose I O pin or as a MibSPI functional pin 0 SPISIMO pin is ...

Page 72: ...a general purpose I O pin or as a MibSPI functional pin 0 SPICLK pin is a GPIO 1 SPICLK pin is a MibSPI functional pin Bit 0 ENAFUN SPIENA function Determines whether the SPIENA pin is to be used as a general purpose I O pin or as a MibSPI functional pin 0 SPIENA pin is a GPIO 1 SPIENA pin is a MibSPI functional pin ...

Page 73: ...is configured to run in MibSPI mode In this mode the addi tional features are available If no multi buffer RAM is attached to the MibSPI kernel only the features implemented in the kernel are avail able 0 The MibSPI runs in compatibility mode i e in this mode the MibSPI is fully code compliant to the standard TMS470SPI All enhanced fea tures are deactivated Bits 31 16 040h Reserved U Bits 15 1 0 R...

Page 74: ...of ICLK cycles C2TDELAY can be configured between 2 and 33 ICLK cycles Figure 15 Example tC2TDELAY 8 ICLK cycles The setup time value is calculated as shown in Equation 1 Equation 1 Chip Select Active to Transmit Start Delay Time Example ICLK 25 MHz C2TDELAY 06h tC2TDELAY 320 ns When the chip select signal becomes active the slave has to prepare data transfer within 320 ns Bits 31 29 28 24 23 21 2...

Page 75: ...s After the last data bit or parity bit is being transferred the chip select signal is held active for 120 ns Bits 15 8 T2EDELAY Transmit data finished to ENA pin inactive time out T2EDELAY is used in master mode only It defines a time out value as a multiple of SPI clock before the ENAble signal has to become inactive and after the CS becomes inactive The SPI clock depends on which data format is...

Page 76: ...ates an ENA signal as a hardware handshake response C2EDELAY defines the maximum time between the MibSPI activates the chip select signal and the addressed slave has to respond by activating the ENA signal C2EDELAY defines a time out value as a multiple of SPI clocks The SPI clock depends on whether data format 0 or data format 1 is selected If the slave device is not responding with the ENA signa...

Page 77: ...d as following Equation 4 Chip select active to ENA signal active time out Value Example SPIclock 8 Mbit s C2EDELAY 30h tC2EDELAY 6ms The slave device has to active the ENA signal within 6 ms after the MibSPI has activated the chip select signal SCS otherwise the TIMEOUT flag is set and a interrupt is asserted if enabled SCS ENA CLK SOMI tC2EDELAY tC2EDELAY C2EDELAY SPIclock ...

Page 78: ...et a chip select pattern which deselect all the SPI slaves 1 If CSDEFx is set to 1 the corresponding chip select is set to 1 when no transfer occurs 0 If CSPOLx is set to 0 the corresponding chip select is set to 0 when no transfer occurs Bits 31 16 048h Reserved U Bits 15 8 Reserved U Bits 7 6 5 4 3 2 1 0 CSDEF7 CSDEF6 CSDEF5 CSDEF4 CSDEF3 CSDEF2 CSDEF1 CSDEF0 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 R...

Page 79: ... applied is equal to WDELAY PICLK 2 PICLK Bit 23 SHIFTDIRx Shift direction for data format x With bit SHIFTDIRx the shift direction for data format x x 1 2 3 can be selected 1 Data format x shift direction Least significant bit is shifted out first 0 Data format x shift direction Most significant bit is shifted out first Bit 22 PARPOLx Parity polarity even or odd PARPOLx can be modified in privile...

Page 80: ...in the corresponding control field The parity type even or odd can be selected via the PARPOL bit 0 No parity generation verification is performed for this data format Bit 14 PHASEx SPI Data format x clock delay PHASEx defines the clock delay of data format x PHASEx can be modified in privilege mode only 1 If PHASEx is set to 1 the SPI clock signal is delayed by a half SPI clock cycle versus the t...

Page 81: ...s configured as slave PRESCALEx DOES NOT NEED to be configured The clock rate for data format x can be calculated as shown in Equation 5 Equation 5 SPI clock rate for data format x When PRESCALEx is set to zero 0 the SPI clock rate is ICLK 2 Bits 4 0 CHARLENx SPI data format x data word length CHARLENx defines the word length of data format x Legal values are 0x02 data word length 2 bit to 0x10 da...

Page 82: ...pt level 1 A parity error interrupt PARITYERR 1 is mapped to interrupt line INT1 0 A parity error interrupt PARITYERR 1 is mapped to interrupt line INT0 Bit 24 TIMEOUTLVL ENA signal time out interrupt level 1 An interrupt on a time out of the ENA signal TIMEOUT 1 is mapped to interrupt line INT1 0 An interrupt on a time out of the ENA signal TIMEOUT 1 is mapped to interrupt line INT0 Bits 31 28 27...

Page 83: ... 16 TIMEOUTENA Enables interrupt on ENA signal time out 1 Enables an interrupt on a time out of the ENA signal TIMEOUT 1 0 No interrupt asserted upon ENA signal time out Bits 15 12 Reserved Bit 11 BITERR Mismatch of internal transmit data and transmitted data This flag is read clear only flag i e reading the flag will automatically clear it 1 A bit error occurred The MibSPI samples the signal of t...

Page 84: ...ction 7 19 bit 10 During reception of the data word the parity generator calculates the reference parity and compares it to the received parity bit In the event of a mismatch the PARITYERR flag is set and an interrupt is asserted if PARERRENA is set 0 No parity error detected Bit 8 TIMEOUT Time out due to non activation of ENA signal This flag is read clear only flag i e reading the flag will auto...

Page 85: ... has been finished 0 No interrupt at the end of a transfer group transfer Bits 15 0 INTENSUSx Transfer group interrupt enable when transfer suspended 1 A interrupt is asserted when a transfer from transfer group x is sus pended 0 No interrupt due to suspending of a transfer group transfer Bits 31 30 29 28 27 26 25 24 05Ch INTENRDY15 INTENRDY14 INTENRDY15 INTENRDY12 INTENRDY11 INTENRDY10 INTENRDY9 ...

Page 86: ...ransfer finished interrupt of the transfer group x is mapped to inter rupt line INT0 Bits 15 0 INTLVLSUSx Transfer group interrupt level for transfer suspended event 1 A transfer suspended interrupt of the transfer group x is mapped to interrupt line INT1 0 A transfer suspended interrupt of the transfer group x is mapped to interrupt line INT0 Bits 31 30 29 28 27 26 25 24 060h INTLVL RDY15 INTLVL ...

Page 87: ...om transfer group x occurred No matter whether the interrupt is enabled or disabled INTENRDYx don t care or whether the interrupt is mapped to line INT0 or INT1 INTFLGRDYx is set right after the transfer from transfer group x is finished Writing a one 1 in bit field will clear the corresponding bit flag 0 No transfer finished interrupt occurred since last clearing of the flag INTFLGRDYx Writing a ...

Page 88: ...NTFLGSUSx 1 A transfer suspended interrupt from transfer group x occurred No matter whether the interrupt is enabled or disabled INTENSUSx don t care or whether the interrupt is mapped to line INT0 or INT1 INTFLGSUSx is set right after the transfer from transfer group x is sus pended Writing a one 1 in bit field will clear the corresponding bit flag 0 No transfer suspended interrupt occurred since...

Page 89: ...CT0 Interrupt vector for interrupt line INT0 INTVECT0 returns the vector of the pending interrupt at interrupt line INT0 If more than one interrupt is pending INTVECT0 always references the highest prior interrupt source first The transfer group with the smallest number has the highest priority Reading INTVECT0 automatically updates the TGINTVECT0 register with the interrupt vector coming next in ...

Page 90: ...by INTVECT0 has asserted an interrupt because all data from the whole transfer group has been transferred INTVECT0 5 1 Description 00000b no interrupt pending 00001b Pending interrupt of transfer group 0 Refer to the flag SUS PEND to determine the interrupt type transfer suspended transfer finished 00010b Pending interrupt of transfer group 1 Refer to the flag SUS PEND to determine the interrupt t...

Page 91: ...th the interrupt vector coming next in the interrupt priority chain and the corresponding type SUSPEND flag Error interrupts have lowest priority Bits 0 SUSPEND Transfer suspended or transfer finished interrupt Every time TGINTVECT1 is read by the host the corresponding interrupt flag of the referenced transfer group is cleared and TGINTVECT1 is updated with the vector coming next in the priority ...

Page 92: ...g SUS PEND to determine the interrupt type transfer suspended transfer finished 00011b Pending interrupt of transfer group 2 Refer to the flag SUS PEND to determine the interrupt type transfer suspended transfer finished 00001b x Pending interrupt of transfer group x x 0 15 Refer to the flag SUSPEND to determine the interrupt type transfer sus pended transfer finished 10001b Error interrupt pendin...

Page 93: ...ransfer groups e g falling edge rising edge and both edges Bit 31 TICKENA Tick counter enable 1 The MibSPI internal tick counter is enabled and is clocked by the clock source selected by CLKCTRL 1 0 When the tick counter is enabled it starts down counting from its current value When TICKENA goes from 0 to 1 the tick counter is automatically loaded with the TICKVALUE 0 The MibSPI internal tick coun...

Page 94: ...e MibSPI internal tick counter Bits 27 16 Reserved Bits 15 0 TICKVALUE Initial value for tick counter TICKVALUE stores the initial value for the tick counter The tick counter is loaded with TICKVALUE every time an under flow condition occurs and every time the PRELOAD flag is set by the host CLKCTRL 1 0 Description 00b SPICLK of Data word format 0 is selected as clock source of tick counter 01b SP...

Page 95: ...TART x 1 1 The 15th transfer group has no subsequent transfer group i e no end address is inherently defined Therefore LPEND has to be programmed to specify explicitly the end address of the 15th transfer group Note LPEND allows SW compatibility for MibSPI variants Due to software compatibility reasons the last transfer group end address has to be configurable otherwise a super set MibSPI can t em...

Page 96: ... transfer mode 0 The corresponding transfer group is disabled Disabling a transfer group while a transfer is ongoing will finish the ongoing buffer transfer but not the whole group transfer Bits 30 ONESHOT Single transfer group transfer 1 A transfer from the corresponding transfer group will be performed only once one shot after a valid trigger event at the selected trigger source After the transf...

Page 97: ...atter whether the concerned transfer group is in transfer mode or not The trigger events have priority over the ongoing transfer 0 If a trigger event occurs during a transfer from the concerned transfer group the event is ignored and is not stored internally The transfer group transfer has priority over additional trigger events Bits 28 TGTD Transfer group triggered This bit is read only 1 The tra...

Page 98: ...e group transfer restarted at the beginning If ONESHOT is set the transfer is performed only once If the logic level changes to low 0 during an ongoing group transfer the whole group transfer will be sus pended 0110b low active Repetitive group transfer while trigger is low While the selected trigger source TRIGSRC is at a logic low level 0 the group transfer is continued and at the end of one res...

Page 99: ...wait PCURRENT keeps the address of the next buffer After the transfer group resumes from suspend to wait mode the next buffer will be transferred i e no buffer data is multiply transferred or not at all transferred due to suspend to wait mode TRIGSRC 3 0 Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0 Source has to be defined individually for each Microcontroller deriva...

Page 100: ...rolled by the MibSPI and not by the DMA controller After ICOUNT 1 transfers the enable bits RXDMAENA and TXDMAENA are automatically cleared by the MibSPI hence no more DMA requests are generated In conjunction with NOBRK a burst transfer can be initiated without any other transfer through another buffer 0 The length of the block transfer is fully controlled by the DMA control ler The enable bits R...

Page 101: ...MA channel If RXDMAENA and TXDMAENA are both set then TXDMACH 3 0 shall differ from RXDMACH 3 0 and shall differ from any other used physical DMA channel Otherwise unexpected interference may occur Bit 15 RXDMAENA Receive data DMA channel enable 1 The physical DMA channel for the receive path is enabled The first DMA request pulse is generated after the first transfer from the refer enced buffer B...

Page 102: ...ers from other active buffers or transfer groups Every time the sequencer checks the DMA buffer it performs one trans fer and then steps to the next buffer Bits 12 8 ICOUNT Initial number of DMA transfers ICOUNT 4 0 is used to preset the transfer counter COUNT 4 0 Every time COUNT 4 0 hits zero it is reloaded with ICOUNT 4 0 The real number of transfer equals ICOUNT 4 0 plus one If ONESHOT is set ...

Page 103: ...the transmit field and the high half word xxxx xx10b is allocated by the corresponding control field The receive fields are read only and can be accessed through the address range 202h to 3FFh The corresponding status fields are mapped into the same address range 200h to 3FDh i e the receive fields are interleaved with the status fields When performing a 32 bit read from a receive buffer the high ...

Page 104: ...ive data can be stored in RXDATA without data loss overwrite protect mode 0 1 1 The sequencer skips the buffer until the corresponding TXFULL flag and RXEMPTY flag are set i e new transmit data available and previous receive data consumed read by the host 1 0 0 Sequencer initiates a transfer every time it checks this buffer continuous mode Data transmit are retransmitted if it has not been updated...

Page 105: ...the previous one the active chip select signals is extended until end of a transfer with CSHOLD cleared or until the chip select information changes If CSHOLD is set in the control field of the last buffer to be transferred then the corresponding chip select signal stays active until a new trans fer is initiated 0 The chip select signal is deactivated at the end of a transfer after the T2CDELAY ti...

Page 106: ...nd 8 bit read write access is supported In the event of a 32 bit access the low half word addresses the transmit field and the high half word addresses the corresponding control field DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected see section 7 3 and section 7 4 for this buffer 0 1 Data word format 1 is selected see section 7 19 for this buffer 1 0 Data word format 2 is selected see ...

Page 107: ...shed and the received data is copied into the corresponding RXDATA field while RXEMPTY flag is already cleared RXOVR is set 1 A receive data overrun condition occurred since last time reading the status field 0 No receive data overrun condition occurred since last time reading the status field Bit 13 TXFULL Transmit data buffer full This flag is read only flag Writing into the corresponding TXDATA...

Page 108: ...nchronized The master monitors the ENA sig nal coming from the slave device and sets the DESYNC flag if ENA is deactivated before the last reception point or after the last bit is trans mitted plus tT2EDELAY see Section 7 17 If DESYNCENA is set an interrupt is asserted De synchronization can occur if a slave device misses a clock edge coming from the master or is detecting an addi tional clock edg...

Page 109: ...t a data transfer from this buffer 0 No ENA signal time out occurred Bit 8 Reserved Bits 7 0 LCSNR Last chip select number LCSNR in the status field is a copy of CSNR in the corresponding control field It defines the chip select that has been activated during the last data transfer from the corresponding buffer LCSNR is copied from the Kernel MibSPI after transmission during write back of received...

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