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Control Registers and RAM
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
101
Bit 9
TIMEOUT.
Time-out due to non-activation of ENA signal.
This flag is read/clear only flag, i.e. reading the flag will automatically clear it.
1 =
An ENA signal time-out occurred. The MibSPI generates a time-out
because the slave hasn’t responded in time by activating the ENA sig-
nal after the chip select signal has been activated. If a time-out condi-
tion is detected the corresponding chip select is deactivated
immediately and the TIMEOUT flag is set. In addition the TIMOUT flag
in the status field of the corresponding buffer is set. The transmit
request of the concerned buffer is cleared, i.e. the MibSPI doesn’t re-
start a data transfer from this buffer.
0 =
No ENA-signal time-out occurred.
Bit 8
Reserved.
Bits 7:0
LCSNR.
Last chip select number.
LCSNR in the status field is a copy of CSNR in the corresponding control
field. It defines the chip select that has been activated during the last data
transfer from the corresponding buffer.
LCSNR is copied from the Kernel MibSPI after transmission during write back
of received data.
7.30.4
Receive Field
Bits 15:0
RXDATA.
Receive data field.
Receive data can be read through RXDATA. The received data is
automatically stored right-aligned into RXDATA, independent from the
selected data word length. 16-bit and 8-bit accesses are supported. In the
event of a 32-bit read access the low half-word contains the receive data and
the high half-word contains the corresponding status field.
Bits
15
0
base1+
200h...
3FFh
RXDATA
R-x
R = Read, W = Write, C = Clear, U = Undefined,
-n
= Value after reset, x = indeterminate
Summary of Contents for TMS470R1x
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