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MibSPI Operation Modes
10
SPIENA pin will allow the master SPI to drive the clock pulse stream;
otherwise, the master will hold the clock signal.
To use the SPIENA as a WAIT signal pin, the slave SPIENA pin must be
configured as functional (SPIPC6.0 = 1). If the SPIENA pin is in high-z mode
(ENABLE_HIGHZ = 1), the slave will put SPIENA into the high-impedance
once it receives a new character. If the SPIENA pin is in push-pull mode
(ENABLE_HIGHZ = 0), the slave will drive SPIENA high once it receives a
new character. The slave will drive SPIENA low again after new data is written
to the slave shift register (SPIDAT0).
Figure 4.
MibSPI Four-Pin Option with SPIENA
2.4
MibSPI Operation; Five-Pin Option (Hardware Handshaking)
To use the hardware handshaking mechanism, both the SPIENA pin and
SPISCS [7:0] pin must be configured as functional pins.
Compatibility mode
In the master SPI (CLKMOD = 1), the SPIENA pin is configured as a
functional input. If configured as a slave SPI, the SPIENA pin is configured as
a functional output. If the SPIENA pin is in high-z mode (ENABLE_HIGHZ =
1), the slave SPI will put this signal into the high-impedance state if it receives
a new character from the master or if the slave becomes de-selected by the
master (SPISCS goes high). The slave will drive the signal SPIENA low when
MibSPI four pin option (2)
Master
Slave
(Master = 1 ; CLKMOD = 1)
(Master = 0 ; CLKMOD = 0)
SPIDAT0
SPIDAT0
MSB
LSB
MSB
LSB
Write to
SPIDAT0
SPISOMI
SPISIMO
SPISOMI
SPISIMO
SPICLK
SPICLK
SPIENA
SPIENA
Write to
Write to SPIDAT0 (SLAVE)
Write to SPIDAT0 (Master)
SPICLK
SPISIMO
SPISOMI
SPIENA
Summary of Contents for TMS470R1x
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