
92 User Manual
Table 1 Menu Explanations of the CS Type Parameters
Function
Menu
Settings
Explanation
CS Type
~CS
low voltage level of CS signal is available
CS
high voltage level of CS signal is available
CLK Timeout
If the time between two edges of clock signal is less than (or
equal to) the value of timeout, the signal between the two edges
is treated as a frame. The range of clock timeout is 100ns-5ms.
9.
Press the
Bit Order
softkey to select the bit order (
LSB
or
MSB
).
Summary of Contents for T3DSO1000
Page 1: ...User Manual T3DSO1000 T3DSO1000A Series Digital Oscilloscope...
Page 62: ...44 User Manual Figure 16 x Interpolation Figure 17 Sinx x Interpolation...
Page 90: ...72 User Manual Figure 32 Relative Window Trigger...
Page 92: ...74 User Manual Figure 33 Interval Trigger...
Page 98: ...80 User Manual Universal Knob to select the desired value Figure 37 Pattern Trigger...
Page 118: ...100 User Manual Figure 50 UART Trigger...
Page 145: ...User Manual 127 function output Figure 63 Square Root...
Page 205: ...User Manual 187 Figure 100 Option Information...