ST STM32L4 5 Series, Reference Manual, Page: 858 / 1830

Hash processor (HASH) RM0351
858/1830 DocID024597 Rev 5
this digest computation. To launch the final digest computation, the software must
set MDMAT bit to 0 before the last DMA transfer in order to trigger the final digest
computation as it is done for single DMA transfers (see description before).
4. Once computed, the digest can be read from the output registers as described in
Table 181 .
For more information about HMAC detailed instructions, refer to Section 29.3.7: HMAC
operation .
29.3.6 Message padding
Overview
When computing a condensed representation of a message, the process of feeding data
into the hash processor (with automatic partial digest computation every 512-bit block) loops
until the last bits of the original message are written to the HASH_DIN register.
As the length (number of bits) of a message can be any integer value, the last word written
to the hash processor may have a valid number of bits between 1 and 32. This number of
valid bits in the last word, NBLW, has to be written to the HASH_STR register, so that
message padding is correctly performed before the final message digest computation.
Padding processing
Detailed padding sequences with DMA is enabled or disabled are described in
Section 29.3.5: Message digest computing .
Padding example
As specified by Federal Information Processing Standards PUB 180-1 and PUB 180-2,
message padding consists in appending a “1” followed by
k “0”s, itself followed by a 64-bit
integer that is equal to the length L in bits of the message. These three padding operations
generate a padded message of length L + 1 + k + 64, which by construction is a multiple of
512 bits.
For the hash processor, the “1” is added to the last word written to the HASH_DIN register at
the bit position defined by the NBLW bitfield, and the remaining upper bits are cleared (“0”s).
Table 181. Hash processor outputs
Algorithm Valid output registers Most significant bit Digest size (in bits)
MD5
HASH_H0 to
HASH_H3
HASH_H0[31]
128
SHA-1
HASH_H0 to
HASH_H4
HASH_H0[31]
160
SHA-224
HASH_H0 to
HASH_H6
HASH_H0[31]
224
SHA-256
HASH_H0 to
HASH_H7
HASH_H0[31]
256