ST STM32L4 5 Series, Reference Manual, Page: 419 / 1830

DocID024597 Rev 5 419/1830
RM0351 Flexible static memory controller (FSMC)
471
can be read/written from/to the Flash memory), Write transactions and Read
transactions are allowed (the controller reads the entire 16-bit memory word and
uses only the required byte).
Wrap support for NOR Flash/PSRAM
Wrap burst mode for synchronous memories is not supported. The memories must be
configured in linear burst mode of undefined length.
Configuration registers
The FMC can be configured through a set of registers. Refer to Section 16.5.6 , for a
detailed description of the NOR Flash/PSRAM controller registers. Refer to Section 16.6.7 ,
for a detailed description of the NAND Flash registers.
16.4 External device address mapping
From the FMC point of view, the external memory is divided into fixed-size banks of
256 Mbytes each (see
Figure 37 ):
•
Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is
split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows:
–
Bank 1 - NOR/PSRAM 1
– Bank 1 - NOR/PSRAM 2
– Bank 1 - NOR/PSRAM 3
– Bank 1 - NOR/PSRAM 4
•
Bank 3 used to address NAND Flash memory devices.The MPU memory attribute for
this space must be reconfigured by software to Device.
For each bank the type of memory to be used can be configured by the user application
through the Configuration register.