DocID024597 Rev 5
RM0351
USB on-the-go full-speed (OTG_FS)
1774
1.
host attempts to send data (OUT token) to an endpoint.
2. When the core receives the OUT token on the USB, it stores the packet in the Rx FIFO
because space is available there.
3. After writing the complete packet in the Rx FIFO, the core then asserts the RXFLVL
interrupt (in OTG_GINTSTS).
4. On receiving the PKTCNT number of USB packets, the core internally sets the NAK bit
for this endpoint to prevent it from receiving any more packets.
5. The application processes the interrupt and reads the data from the Rx FIFO.
6. When the application has read all the data (equivalent to XFRSIZ), the core generates
an XFRC interrupt (in OTG_DOEPINTx).
7. The application processes the interrupt and uses the setting of the XFRC interrupt bit
(in OTG_DOEPINTx) to determine that the intended transfer is complete.
IN data transfers
•
Packet write
This section describes how the application writes data packets to the endpoint FIFO when
dedicated transmit FIFOs are enabled.
1.
The application can either choose the polling or the interrupt mode.
–
In polling mode, the application monitors the status of the endpoint transmit data
FIFO by reading the
OTG_
DTXFSTSx register, to determine if there is enough
space in the data FIFO.
–
In interrupt mode, the application waits for the TXFE interrupt (in OTG_DIEPINTx)
and then reads the OTG_DTXFSTSx register, to determine if there is enough
space in the data FIFO.
–
To write a single non-zero length data packet, there must be space to write the
entire packet in the data FIFO.
–
To write zero length packet, the application must not look at the FIFO space.
2. Using one of the above mentioned methods, when the application determines that
there is enough space to write a transmit packet, the application must first write into the
endpoint control register, before writing the data into the data FIFO. Typically, the
application, must do a read modify write on the OTG_DIEPCTLx register to avoid
modifying the contents of the register, except for setting the Endpoint Enable bit.
The application can write multiple packets for the same endpoint into the transmit FIFO, if
space is available. For periodic IN endpoints, the application must write packets only for one
microframe. It can write packets for the next periodic transaction only after getting transfer
complete for the previous transaction.
•
Setting IN endpoint NAK
Internal data flow: