Schweitzer Engineering SEL-351P, Quick Start Manual

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Date Code 990430 Loss-of-Potential, Load Encroachment, and Directional Element Logic 4-9
SEL-351P Manual Técnico
Note that Figure SECTION 4: .5 has extra internal enable 32QE, which is used in the directional
element logic that controls negative-sequence and phase overcurrent elements (see
Figure SECTION 4: .17).
The settings involved with internal enables 32QGE and 32VE in Figure SECTION 4: .5 and
Figure SECTION 4: .6 (e.g., settings a2, k2, a0) are explained in the following subsection
Directional Control Settings .
The zero-sequence voltage-polarized, neutral-current directional element is a sensitive-earth-fault
(SEF) directional element. If V is in the setting ORDER, and no other internal enable is asserted,
32NE may be asserted as shown in Figure SECTION 4: .7. Neutral current will then be used in
determining fault direction.
Best Choice Ground Directional ™ Logic
Refer to Figure SECTION 4: .4 and Figure SECTION 4: .8.
The internal enables 32QGE and 32VE and setting ORDER are used in the Best Choice Ground
Directional logic in Figure SECTION 4: .8. The Best Choice Ground Directional logic
determines which directional element should be enabled to operate. The neutral ground and
residual ground overcurrent elements set for directional control are then controlled by this
enabled directional element. If V is in the setting ORDER, and no other internal enable is
asserted, 32NE may be asserted as shown in Figure SECTION 4: .7. Neutral current will then be
used in determining fault direction.
Directional Elements
Refer to Figure SECTION 4: .4, Figure SECTION 4: .9, Figure SECTION 4: .10, and
Figure SECTION 4: .11.
The enable output of Best Choice Ground Directional logic in Figure SECTION 4: .8, and the
internal enables in Figure SECTION 4: .5, Figure SECTION 4: .6, and Figure SECTION 4: .7
determine which directional element will run.
Additionally, note that if enable setting ELOP = Y or Y1 and a loss-of-potential condition occurs
(Relay Word bit LOP asserts), the negative-sequence voltage-polarized and zero-sequence
voltage-polarized directional elements are disabled (see Figure SECTION 4: .9,
Figure SECTION 4: .10, and Figure SECTION 4: .11).
Refer to Figure SECTION 4: .1 and accompanying text for more information on loss-of-
potential.
Directional Element Routing
Refer to Figure SECTION 4: .4, Figure SECTION 4: .12, and Figure SECTION 4: .13.
The negative-sequence and zero-sequence polarized, residual-current directional element outputs
are routed to the forward (Relay Word bit 32GF) and reverse (Relay Word bit 32GR) logic points
and then on to the direction forward/reverse logic in Figure SECTION 4: .14.