Date Code 990215
Factory-Set Logic
1-37
SEL-351P Manual Técnico
51P1
Relay
Word
Bits
51P2
51G1
51G2
51N1
51N2
67N3
TRIP
at least one fast curve,
delay curve, or SEF
element is picked up
SEL
OGIC
Setting
79BRS
(block
reset
timing)
DWG: M351R029
Figure SECTION 1: .26:
Block Reset Timing Logic
S
EQUENCE
C
OORDINATION
Refer to subsection
Sequence Coordination Setting (79SEQ)
in
Section 6: Close and Reclose
Logic
for background on the operation of the 79SEQ setting.
See Figure SECTION 1: .27. Enable sequence coordination with EZ setting:
Sequence coordination = Y (asserts Relay Word bit SEQC to logical 1)
Besides the Sequence coordination EZ setting, the factory-set sequence coordination logic
requires both the following be true:
•
SEL-351P is in the Reset state (Relay Word bit 79RS = logical 1)
•
Fast curve - phase or Fast curve - ground is picked up (Relay Word bit pickup indicator
51P1 = logical 1, 51G1 = logical 1, or 51N1 = logical 1, respectively)
Then the sequence coordination SEL
OGIC
setting 79SEQ asserts to logical 1.
Relay
Word
Bits
79RS
51P1
51G1
51N1
reset state
phase
ground
sequence coordination enabled with
setting ESEQ (or corresponding EZ
setting Sequence coordination)
SEQC
fast phase or ground
curve picked up
SEL
OGIC
Setting
79SEQ
(input into
sequence
coordination
logic)
DWG: M351R027
Figure SECTION 1: .27:
Sequence Coordination Logic
Summary of Contents for SEL-351P
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