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R&S AFQ100A
Output Block
1401.3084.32 4.65
E-3
The output clock source and frequency are set in the
Clock
section.
Note:
The section
Clock
section is displayed only if PORT2 is activated.
Clock (Interface clock
= memory clock)
(Port 2 only)
For configuring the clock settings see section
, on page
Slope - Digital Output
(Port2 only)
Sets the polarity of the active clock for triggering digital signal
transmission via Port2. Clock and data are in phase. Either the rising
or the falling edge of the data clock can be selected. .
Positive
The rising edge of the clock signal is active.
Remote-control commands:
SOUR:OUTP:DIG:CLOC:SLOP POS
Negative
The falling edge of the clock signal is active.
Remote-control commands:
SOUR:OUTP:DIG:CLOC:SLOP NEG