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16
Node Address Settings and I/O Allocation
Section 2-2
2-2-3
I/O Allocation to the Slice I/O Terminal’s Master Unit
The Slice I/O Terminal’s I/O data is allocated in the I/O memory of the CPU
Unit in which the Master Unit is mounted and the I/O memory location is
determined by the DeviceNet Communications Unit’s DeviceNet node
address.
The user can set the Slice I/O Terminal’s allocated data freely with a
DeviceNet Configurator.
E
Connected order
CPU Unit
CS/CJ-series
DeviceNet Unit
I/O memory
A
B
C
D
E
DeviceNet
Communications
Unit
A
B
C
D
Slice I/O Terminals (Slaves)
Data is allocated to I/O memory in the order
that the Units are connected, from lowest to
highest.
I/O Units with bit allocation are allocated data
from the rightmost to leftmost bit, in 2-bit units.
I/O Units with word allocations are allocated
data from the lower to higher word address.
0
8
16
Order of allocation
(1) Communications Unit status
(2) Each Slice I/O Unit's I/O data.
(3) Slice I/O Unit network
participation status.
Summary of Contents for SMARTSLICE - 04-2008
Page 1: ...DeviceNet Communications Unit Cat No W454 E1 03 SmartSlice GRT1 DRT OPERATION MANUAL ...
Page 2: ...SmartSlice GRT1 DRT DeviceNet Communications Unit Operation Manual Revised April 2008 ...
Page 3: ...iv ...
Page 5: ...vi ...
Page 13: ...xiv ...
Page 27: ...8 Basic Operating Procedure Section 1 5 ...
Page 57: ...38 Unit Functions Section 2 3 ...
Page 101: ...82 DeviceNet Explicit Messages Appendix A ...
Page 113: ...94 Standard Models Appendix C ...
Page 115: ...96 Power Consumption Tables Appendix D ...
Page 117: ...98 I O Current Consumption Appendix E ...
Page 119: ...100 Glossary ...