APPENDICES
APP
−
80
MELSEC-A
Table 2.6 Instruction Processing Time of CPUs (Continue)
Processing Time (
µ
s)
An
AnN, A73
A3N Board
A3V A3H
A3M
A2A,
A2U
A3A,
A3U, A4U
D, R
D, R
R
R
Instruction
Condi-
tion
D
Other
than
X, Y
X, Y
R D,
R
Other
than
X, Y
X, Y
Other
than
X, Y
X, Y
Other
than
X, Y
X, Y
n=1
439 524 3347 300 400 490 237 261 178 196
FROM
FROMP
n=1000
6609 2358 12605 5050 5230 3130 5749 2789 4312 2092
n=1
449 529 3051 300 410 610 244 266 183 199
DFRO
DFROP
n=500
6609 2109 12595 5050 5270 1900 5669 1669 4252 1252
n=1
449 539 3247 300 410 520 243 266 182 200
TO
TOP
n=1000
6609 3918 22590 5050 5120 3300 5773 2117 4330 1588
n=1
454 544 3523 300 410 520 240 266 180 199
DTO
DTOP
n=500
6609 1609 19340 5050 5120 2200 5747 1501 4310 1126
R: Refresh mode, D: Direct mode
The processing time shown above is the value when the AD71 is used as special function modules.
*1: n3=1000 for the A3V and A3H.
n3=1000 when other than X and Y is specified with other CPU.
n3=112 when X and Y are specified.
*2: n3=500 for the A3V and A3H.
n3=500 when other than X and Y is specified with other CPU.
n3=56 when X and Y are specified.
POINTS
(1) All the application instructions indicated above are used without index
qualification.
(2) When unexecuted, any instruction is processed during the following time:
An................................................... (Number of steps + 1) x 1.3 (
µ
s)
AnN, A3V, A73 and A3N board ...... (Number of steps + 1) x 1.0 (
µ
s)
A3H and A3M ................................ (Number of steps + 1) x 0.2 (
µ
s)
A2A and A2U .................................(Number of steps + 4) x 0.2 (
µ
s)
A3A, A3U and A4U ........................ (Number of steps + 4) x 0.15 (
µ
s)
Summary of Contents for MELSEC-A series
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