Mitsubishi MELSEC-A series, Programming Manual

Page: 32 / 508

2. INSTRUCTIONS
2
−
16
MELSEC-A
2.2.4 Application instructions
(1) Logical operation instructions
Table 2.17 Logical Operation Instructions
Classi-
fication Un
it
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Nu
m
b
e
r
of steps
Inde
x
S
ubset
Applicable CPU Page
WAND 5
● ●
!
7-3
WANDP
(D) AND (S)
→
(D)
5
● ●
!
7-3
WAND 7
●
!
7-3
16 bi
ts
WANDP
(S1) AND (S2)
→
(D)
7
●
!
7-3
DAND 9
●
!
7-3
Logical
product
32 bi
ts
DANDP
(D+1, D) AND (S+1, S)
→
(D+1,D)
9
●
!
7-3
WOR 5
● ●
!
7-8
WORP
(D) OR (S)
→
(D)
5
● ●
!
7-8
WOR 7
●
!
7-8
16bi
ts
WORP
(S1) OR (S2)
→
(D)
7
●
!
7-8
DOR 9
●
!
7-8
Logical
sum
32 bi
ts
DORP
(D+1, D) OR (S+1, S)
→
(D+1, D)
9
●
!
7-8
WXOR 5
● ●
!
7-12
WXORP
(D) XOR (S)
→
(D)
5
● ●
!
7-12
WXOR 7
●
!
7-12
16 bi
ts
WXORP
(S1) XOR (S2)
→
(D)
7
●
!
7-12
DXOR 9
●
!
7-12
Exclu-
sive
logical
sum
32 bi
ts
DXORP
(D+1, D) XOR (S+1, S)
→
(D+1, D)
9
●
!
7-12
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1