7. APPLICATION INSTRUCTIONS
7
−
132
MELSEC-A
Execution Conditions
POINT
When the status latch (SLT) instruction is executed, the scan time of program-
mable controller CPU increases as shown in the following table.
Latch of Only
Device Memory
Latch of Both Device
Memory and File Register
A2(-S1), A2C
A0J2H, A52G
11 ms
21 ms
A3
11 ms
31 ms
A2N(-S1), A1S(-S1)
A1SJ(-S3), A2S)-S1)
8.5 ms
25 ms
A3N, A73, A3N board
8.5 ms
37 ms
A3H, A3M
4.1 ms
10.4 ms
A2A(-S1), A2U
A2AS(-S1/S30/S60)
2.9 ms
12.9 ms
A3A, A3U, A4U, A3A
2.2 ms
9.7 ms
A2USH-S1,
A2USH board
1.3 ms
4.5 ms
A1SH, A1SJH
1.5 ms
3.8 ms
A2SH(-S1)
1.4 ms
3.0 ms
A1FX
1.4 ms
3.0 ms
Q02
4.6 ms
6.1 ms
Q02H, Q06H
1.7 ms
2.3 ms
Set the watch dog timer of programmable controller CPU after considering the
above increase in scan time.
OFF
ON
Executed
only once
Status latch command
OFF
Executed only once
Reset command
SLT
SLTR
ON
Executed only once
Summary of Contents for MELSEC-A series
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