Mitsubishi MELSEC-A series, Programming Manual

Page: 33 / 508

2. INSTRUCTIONS
2
−
17
MELSEC-A
Table 2.17 Logical Operation Instructions (Continue)
Classi-
fication Un
it
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Nu
m
b
e
r
of steps
Inde
x
S
ubset
Applicable CPU Page
WXNR 5
● ●
!
7-16
WXNRP
(D) XOR (S)
→
(D)
5
● ●
!
7-16
WXNR 7
●
!
7-16
16 bi
ts
WXNRP
(S1) XOR (S2)
→
(D)
7
●
!
7-16
DXNR 9
●
!
7-16
NOT
exclu-
sive
logical
sum
32 bi
ts
DXNRP
(D+1, D) XOR (S+1, S)
→
(D+1, D)
9
●
!
7-16
NEG 3
●
!
7-20
2’s
comple-
ment
16 bi
ts
NEGP
0- (D)
→
(D)
3
●
!
7-20
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1