Mitsubishi MELSEC-A series, Programming Manual

Page: 27 / 508

2. INSTRUCTIONS
2
−
11
MELSEC-A
Table 2.11 Arithmetic Operation Instruction (Continue)
Classi-
fication Un
it
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Nu
m
b
e
r
of steps
Inde
x
S
ubset
Applicable CPU Page
D
∗
11
● ●
!
6-19
D
∗
P
(S1+1, S1)
×
(S2+1, S2)
→
(D+3, D+2, D+1, D)
11
● ●
!
6-19
D/ 11
● ●
!
6-19
BIN
32bit
multipli-
cation/
division
32 bi
ts
D/P
(S1+1, S1) / (S2+1, S2)
→
Quotient (D+1, D),
Remainder (D+3, D+2)
11
● ●
!
6-19
B+ 7
●
!
6-22
B+P
(D) + (S)
→
(D)
7
●
!
6-22
B+ 9
●
!
6-22
B+P
(S1) + (S2)
→
(D)
9
●
!
6-22
B- 7
●
!
6-22
B-P
(D) - (S)
→
(D)
7
●
!
6-22
B- 9
●
!
6-22
BCD
4-digit
addition/
subtrac-
tion
B
C
D
4-di
gi
ts
B-P
(S1) - (S2)
→
(D)
9
●
!
6-22
DB+ 9
●
!
6-25
DB+P
(D+1, D) + (S+1, S)
→
(D+1, D)
9
●
!
6-25
DB+ 11
●
!
6-25
BCD
8-digit
addition
subtrac-
tion
B
C
D
8-di
gi
ts
DB+P
(S1+1, S1) + (S2+1, S2))
→
(D+1, D)
11
●
!
6-25
DB- 9
●
!
6-25
DB-P
(D+1, D) - (S+1, S)
→
(D+1, D)
9
●
!
6-25
DB- 11
●
!
6-25
BCD
8-digit
addition,
subtrac-
tion
B
C
D
8-di
gi
ts
DB-P
(S1+1, S1) - (S2+1, S)
→
(D+1, D)
11
●
!
6-25
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3
*3
*3
*3
*1