300
Development Tools User’s Guide
Intel
®
IXP2400/IXP2800 Network Processors
Intel XScale® Core Memory Bus Functional Model
Note:
The Issue I/O Request signal is asserted by the Intel XScale
core when a data cache request is for
a memory region with C=0 and B=0 (Uncachable and Unbufferable). The CMB BFM API does not
provide a means of asserting Issue I/O Request, so all swap commands to SRAM or Scratch
memory generate Atomic operations and references to any other address space will be treated as
separate read and write commands.
int
cmbSwapRead32
(char
*chip_name
,
unsigned int
addr
,
unsigned int
byteEnable
)
int
cmbSwapWrite32
(char
*chip_name
,
unsigned int
addr
,
unsigned int
data
,
unsigned int
byteEnable
)
where:
chip_name
:
name of the instantiated IXP2800/IXP2400 instance,
addr
:
32-bit Intel XScale
address,
data
: write
data,
byteEnable
:
mask bit for each byte (1: byte enable, 0: byte masked),
return
value:
request-id or
-1: byteEnable invalid, Write only (CMB_FAIL)
-3: no callback function registered
(CMB_ERROR_NO_CB_REGISTER),
-2: request queue is full (CMB_ERROR_QUEUE_FULL)
The error codes are defined in
Cmb_Client.h
.
C.1.10
cmbBFMRead32 / cmbBFMWrite32
These two functions are provided to support a more generic load/store instructions – i.e. burst
transfers.
int
cmbBFMRead32
(char
*chipName
,
unsigned int
addr
,
unsigned int
size
)
int
cmbBFMWrite32
(char
*chipName
,
unsigned int
addr
,
unsigned int
size
,
unsigned int
byteEnable
,
unsigned int
*data
)
where:
chip_name
:
name of the instatiated IXP2800/IXP2400 instance,
addr
:
32-bit Intel XScale
address,
size
:
size of the request (defined by enum CmbSize),
0: one-byte,
1: 2-byte,
