Intel IXP2400, User Manual

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Development Tools User’s Guide 281
Intel
®
IXP2400/IXP2800 Network Processors
Transactor States
A.7 IXP2400 and IXP2800 Transactor States
In the following command and tables, chip_name is the name the user applies to the chip instance.
In other words, the user replaces chip_name with their own chip_name (if there is one). If the
instance is unnamed, then the chip_name variable is omitted.
For the QDR interface, n is the SRAM channel number, which can be either 0, 1, 2 or 3 (for the
IXP2800). For the IXP2400, n may be 0 or 1.
To connect a foreign model to the QDR interface, you must add the
setup_sram_external_pin_usage
command to the setup script (this must be done for
each channel). The command is not necessary if you want to connect only to the MSF interface.
setup_sram_external_pin_usage(chip_name, lower_address, upper_address);
The lower_address and upper_address denote the range in the sram memory map to use for an
external model.
Table 1. IXP2400 Transactor States for QDR and MSF Pins (Sheet 1 of 3)
Transactor State Names
Datasheet
Signal Name
I/O Description
QDR Interface
chip_name .QDR n _K_H[1:0]
chip_name .QDR n _K_L[1:0]
S n _K[1:0]
S n _K_L[1:0]
Output
Output
Positive and negative clock outputs.
These differential clocks are used as a
reference for Address, Data Out, and
Port Enable.
chip_name .QDR n _C_H[1:0]
chip_name .QDR n _C_L[1:0]
S n _C[1:0]
S n _C_L[1:0]
Output
Output
Positive and negative clock outputs.
chip_name .QDR n _CIN_H[1:0]
chip_name .QDR n _CIN_L[1:0]
S n _CIN[1:0]
S n _CIN_L[1:0]
Input
Input
Positive and negative clock inputs.
These differential clocks are used as a
reference for Data In. They are the
feedback of S
n _C & S n _C_L.
chip_name .QDR n _D_H[7:0] S n _D[7:0] Output Data output bus
chip_name .QDR n _D_H[16:9] S n _D[15:8] Output Data output bus
chip_name .QDR n _D_H[8] S n _D[0] Output
Byte parity for data out. D[0]
corresponds to D[7:0].
chip_name .QDR n _D_H[17] S n _D[1] Output
Byte parity for data out. D[1]
corresponds to D[15:8].
chip_name .QDR n _Q_H[7:0] S n _Q[7:0] Input Data output bus
chip_name .QDR n _Q_H[16:9] S n _Q[15:8] Input Data output bus
chip_name .QDR n _Q_H[8] S n _Q[0] Input
Byte parity for data in. Q[0]
corresponds to Q[7:0].
chip_name .QDR n _Q_H[17] S n _Q[1] Input
Byte parity for data in. Q[1]
corresponds to Q[15:8].
chip_name .QDR n _BWS_L[1:0] S n _BWE_L[1:0] Output
Byte write enables. BW_L[1], BW_L[0]
corresponds to DO[15:8], DO[7:0]
respectively
chip_name .QDR n _RPS_L[1:0] S n _RPE_L[1:0] Output Read Port Enable