Development Tools User’s Guide
299
Intel
®
IXP2400/IXP2800 Network Processors
Intel XScale® Core Memory Bus Functional Model
C.1.8
cmbSetCb
The
cmbSetCb
function provides interface to register a callback function once the CMB BFM
finishes the load transaction.
int
cmbSetCb
(char
*chip_name
,
void (*
fnPtr
)(int
reqId
,
unsigned int
*retData
,
unsigned int
outData
),
unsigned int
inData
)
where:
chip_name
:
Name of the instantiated IXP2800/IXP2400 instance,
fnPtr
:
Pointer to the registered callback function which is invoked by the BFM
when BFM received data valid signal from gasket,
ReqId
:
The request-id which was returned by cmbRead32/cmbWrite32,
retData
:
Pointer to returned read data,
outData
:
The data passed by callee which is the same as inData
return
value:
1 for success, <0 for fail.
If an error is detected, bits 15-0 of the return value will contain the request ID that failed, bits 30-16
of the return value will contain the error code, and bit 31 will be set (making the return value
negative).
Possible failure codes are
•
CMB_ERROR_BUS_ERROR
– Bus Error asserted by the Intel XScale
gasket
•
CMB_ERROR_TIME_OUT
– Timed out waiting for return data.
C.1.9
cmbSwapRead32 / cmbSwapWrite32
These two functions are used for atomic operations, which are programmed to support Intel
XScale
SWP/SWPB instructions.
The
cmbSwapWrite32
is used if no read back is needed for Atomic operation. Intel XScale
can
send a write(store) command with the alias address but without XSOCBI_LOCK asserted. In this
case the callback for the
cmbSwapWrite32
will not wait for read data to be returned, but occur as
soon as the request is acknowledged.
The following rules are enforced by the Intel XScale
Gasket for Atomic commands in Transactor
I/O space:
•
A swap operation to the SRAM/Scratch space and the Issue I/O Request signal
is not
asserted,
then the Gasket generates Atomic operation command to the Transactor.
•
A swap operation to all addresses other than the SRAM/Scratch space will be treated as
separate read and write commands, i.e. no Atomic command is generated.
•
A swap operation to the SRAM/Scratch space and the Issue I/O Request signal
is
asserted will
be treated as separate read and write commands. i.e. no Atomic command is generated.
