282
Development Tools User’s Guide
Intel
®
IXP2400/IXP2800 Network Processors
Transactor States
chip_name
.QDR
n
_WPS_L[1:0]
S
n
_WPE_L[1:0]
Output
Write Port Enable
chip_name
.QDR
n
_A_H[23:0]
S
n
_A[23:0]
Output
Address. Depending on the operating
mode, some of the address pins may
also be used for RPE_L/WPE_L.
chip_name
.QDR
n
_ZQ[1:0]
S
n
_ZQ[1:0]
Input
Drive Strength/Compensation
MSF Interface
chip_name
.PLMS_MR23_CLK
RXCLK23
Input
MSF Receive Clock for channel 2 and
3.
chip_name
.PLMS_MR01_CLK
RXCLK01
Input
MSF Receive Clock for channel 0 and
1.
chip_name
.MSPA_RXENB_WMR23H
RXENB[3:2]
Output
MSF Receive Control Pins for up to 4
Channels.
chip_name
.MSPA_RXENB_WMR01H
RXENB[1:0]
Output
MSF Receive Control Pins for up to 4
Channels.
chip_name
.PAMS_RXSOF_RMR23H
RXSOF[3:2]
Input
chip_name
.PAMS_RXSOF_RMR01H
RXSOF[1:0]
Input
chip_name
.PAMS_RXEOF_RMR23H
RXEOF[3:2]
Input
chip_name
.PAMS_RXEOF_RMR01H
RXEOF[1:0]
Input
chip_name
.PAMS_RXVAL_RMR23H
RXVAL[3:2]
Input
chip_name
.PAMS_RXVAL_RMR01H
RXVAL[1:0]
Input
chip_name
.PAMS_RXERR_RMR23H
RXERR[3:2]
Input
chip_name
.PAMS_RXERR_RMR01H
RXERR[1:0]
Input
chip_name
.PAMS_RXPRTY_RMR23H
RXPRTY[3:2]
Input
chip_name
.PAMS_RXPRTY_RMR01H
RXPRTY[1:0]
Input
chip_name
.PAMS_RXFA_RMR23H
RXFA[3:2]
Input
chip_name
.PAMS_RXFA_RMR01H
RXFA[1:0]
Input
chip_name
.MSPA_RXADDR_WMR01H
RXADDR[3:0]
Output
chip_name
.PAMS_RXPFA_RMR01H
RXPFA
Input
chip_name
.PAMS_RXPADL1_RMR23H
RXPADL[1]
Input
chip_name
.PAMS_RXPADL0_RMR01H
RXPADL[0]
Input
chip_name
.PAMS_RXDATA_RMR01H
RXDATA[15:0]
Input
MSF Receive Data Bus
chip_name
.PAMS_RXDATA_RMR23H
RXDATA[31:16]
Input
MSF Receive Data Bus
chip_name
.PLMS_MT23_CLK
TXCLK23
Input
MSF Transmit Clock for channel 2 and
3.
chip_name
.PLMS_MT01_CLK
TXCLK01
Input
MSF Transmit Clock for channel 0 and
1.
chip_name
.MSPA_TXENB_WMT23H
TXENB[3:2]
Output
MSF Transmit Control Pins for up to 4
Channels.
chip_name
.MSPA_TXENB_WMT01H
TXENB[1:0]
Output
MSF Transmit Control Pins for up to 4
Channels.
chip_name
.MSPA_TXSOF_WMT23H
TXSOF[3:2]
Output
Table 1. IXP2400 Transactor States for QDR and MSF Pins (Continued) (Sheet 2 of 3)
Transactor State Names
Datasheet
Signal Name
I/O
Description